Semiconductor device, method for manufacturing semiconductor device, module, and electronic device

ABSTRACT

A semiconductor device with stable electrical characteristics is provided. Alternatively, a semiconductor device having normally-off electrical characteristics is provided. A semiconductor device includes a gate electrode, a gate insulator, and an oxide semiconductor, the oxide semiconductor contains fluorine in a channel formation region, and a fluorine concentration in the channel formation region is higher than or equal to 1×10 20  atoms/cm 3  and lower than or equal to 1×10 22  atoms/cm 3 . Note that fluorine is added by an ion implantation method.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to, for example, a transistor and asemiconductor device. The present invention relates to, for example, amethod for manufacturing a transistor and a semiconductor device. Thepresent invention relates to, for example, a display device, alight-emitting device, a lighting device, a power storage device, amemory device, an imaging device, a processor, and an electronic device.The present invention relates to a method for manufacturing a displaydevice, a liquid crystal display device, a light-emitting device, amemory device, an imaging device, and an electronic device. The presentinvention relates to a driving method of a display device, a liquidcrystal display device, a light-emitting device, a memory device, animaging device, and an electronic device.

Note that one embodiment of the present invention is not limited to theabove technical field. The technical field of one embodiment of theinvention disclosed in this specification and the like relates to anobject, a method, or a manufacturing method. In addition, one embodimentof the present invention relates to a process, a machine, manufacture,or a composition of matter.

In this specification and the like, a semiconductor device generallymeans a device that can function by utilizing semiconductorcharacteristics. A display device, a light-emitting device, a lightingdevice, a memory device, an imaging device, an electro-optical device, asemiconductor circuit, and an electronic device include a semiconductordevice in some cases.

2. Description of the Related Art

A technique for forming a transistor by using a semiconductor over asubstrate having an insulating surface has attracted attention. Thetransistor is applied to a wide range of semiconductor devices such asan integrated circuit and a display device. Silicon is known as asemiconductor applicable to a transistor.

As silicon which is used as a semiconductor of a transistor, eitheramorphous silicon or polycrystalline silicon is used depending on thepurpose. For example, for a transistor included in a large displaydevice, it is preferable to use amorphous silicon, which can be used toform a film on a large substrate with the established technique. On theother hand, for a transistor included in a high-performance displaydevice where driver circuits are formed over the same substrate, it ispreferred to use polycrystalline silicon, which can form a transistorhaving high field-effect mobility. As a method for formingpolycrystalline silicon, high-temperature heat treatment or laser lighttreatment which is performed on amorphous silicon has been known.

In recent years, transistors using oxide semiconductors (typically,In—Ga—Zn oxide) have been actively developed.

Oxide semiconductors have been researched since early times. In 1988,there was a disclosure of a crystal In—Ga—Zn oxide that can be used fora semiconductor element (see Patent Document 1). In 1995, a transistorincluding an oxide semiconductor was invented, and its electricalcharacteristics were disclosed (see Patent Document 2).

The transistors including oxide semiconductors have different featuresfrom the transistors including amorphous silicon or polycrystallinesilicon. For example, a display device in which a transistor includingan oxide semiconductor is used is known to have small power consumption.An oxide semiconductor film can be formed by a sputtering method or thelike, and thus can be used in a transistor included in a large displaydevice. A transistor including an oxide semiconductor has highfield-effect mobility; therefore, a high-performance display devicewhere driver circuits are formed over the same substrate can beobtained. In addition, there is an advantage that capital investment canbe reduced because part of production equipment for a transistorincluding amorphous silicon can be retrofitted and utilized.

For example, for mass production of semiconductor devices such asdisplay devices, stable electrical characteristics of transistorsincluding an oxide semiconductor are required.

In a transistor including an oxide semiconductor, it is very importantto control oxygen vacancies in the oxide semiconductor. In order toobtain stable transistor characteristics, oxygen vacancies arepreferably reduced as much as possible. As a technique for reducingoxygen vacancies, a method for injecting oxygen into the oxidesemiconductor (see Patent Document 3) can be used.

REFERENCE Patent Documents

-   [Patent Document 1] Japanese Published Patent Application No.    S63-239117-   [Patent Document 2] Japanese Translation of PCT International    Application No. H11-505377-   [Patent Document 3] Japanese Published Patent Application No.    2012-238880

SUMMARY OF THE INVENTION

An object is to provide a transistor with stable electricalcharacteristics. Another object is to provide a transistor havingnormally-off electrical characteristics. Another object is to provide atransistor having a small subthreshold swing value. Another object is toprovide a transistor having a small short-channel effect. Another objectis to provide a transistor having a low leakage current in an off state.Another object is to provide a transistor having excellent electricalcharacteristics. Another object is to provide a transistor having highreliability. Another object is to provide a transistor with highfrequency characteristics.

Another object is to provide a semiconductor device including thetransistor. Another object is to provide a module including any of theabove semiconductor devices. Another object is to provide an electronicdevice including any of the above semiconductor devices or the module.Another object is to provide a novel semiconductor device. Anotherobject is to provide a novel module. Another object is to provide anovel electronic device.

Note that the descriptions of these objects do not disturb the existenceof other objects. In one embodiment of the present invention, there isno need to achieve all the objects. Other objects will be apparent fromand can be derived from the description of the specification, thedrawings, the claims, and the like.

As mentioned above, it is very important to control oxygen vacancies inthe oxide semiconductor. In order to obtain stable transistorcharacteristics, oxygen vacancies are preferably reduced as much aspossible. Moreover, it is also important to form a stable bond so thatthe filled oxygen vacancies are prevented from becoming oxygen vacanciesagain owing to damage in a manufacturing process of a transistor or thelike.

Thus, in one embodiment of the present invention, fluorine is added to achannel formation region of a semiconductor, whereby oxygen vacancies inthe semiconductor are filled, and the oxygen vacancies are filled withfluorine, which forms a stable bond, whereby a transistor having stableand favorable electrical characteristics is provided.

One embodiment of the present invention is a semiconductor deviceincluding a gate electrode, a gate insulator, and an oxidesemiconductor. The oxide semiconductor contains fluorine in a channelformation region.

Another embodiment of the present invention is a semiconductor device inwhich a fluorine concentration in the channel formation region is higherthan or equal to 1×10²⁰ atoms/cm³ and lower than or equal to 1×10²²atoms/cm³.

Another embodiment of the present invention is a semiconductor device inwhich, in the oxide semiconductor, a fluorine concentration in a regionother than the channel formation region is lower than the fluorineconcentration in the channel formation region.

Another embodiment of the present invention is a semiconductor device inwhich the oxide semiconductor contains at least one selected fromindium, zinc, and an element M (an element M is aluminum, gallium,yttrium, or tin).

Another embodiment of the present invention is a module including theabove-described semiconductor device and a printed board.

Another embodiment of the present invention is an electronic deviceincluding the above-described semiconductor device or theabove-described module and a speaker, an operation key, or a battery.

Another embodiment of the present invention is a method formanufacturing a semiconductor device, including the steps of forming anoxide semiconductor over a substrate, forming a source electrode and adrain electrode which are in contact with the oxide semiconductor,adding fluorine to the oxide semiconductor, forming an insulator overthe oxide semiconductor, the source electrode, and the drain electrode,and forming a gate electrode over the insulator.

Another embodiment of the present invention is a method formanufacturing a semiconductor device, including the steps of forming anoxide semiconductor over a substrate, adding fluorine to the oxidesemiconductor, forming a source electrode and a drain electrode whichare in contact with the oxide semiconductor, forming an insulator overthe oxide semiconductor, the source electrode, and the drain electrode,and forming a gate electrode over the insulator.

Another embodiment of the present invention is a method formanufacturing a semiconductor device, including the steps of forming anoxide semiconductor over a substrate, forming a source electrode and adrain electrode which are in contact with the oxide semiconductor,forming an insulator over the oxide semiconductor, the source electrode,and the drain electrode, adding fluorine to the oxide semiconductorthrough the insulator, and forming a gate electrode over the insulator.

Another embodiment of the present invention is a method formanufacturing a semiconductor device, including the steps of forming agate electrode over a substrate, forming an insulator over the gateelectrode, forming an oxide semiconductor over the gate electrode withthe insulator provided therebetween, adding fluorine to the oxidesemiconductor, and forming a source electrode and a drain electrodewhich are in contact with the oxide semiconductor.

Another embodiment of the present invention is a method formanufacturing a semiconductor device, including the steps of forming agate electrode over a substrate, forming an insulator over the gateelectrode, forming an oxide semiconductor over the gate electrode withthe insulator provided therebetween, forming a source electrode and adrain electrode which are in contact with the oxide semiconductor, andadding fluorine to the oxide semiconductor.

Another embodiment of the present invention is a method formanufacturing a semiconductor device in which the fluorine is added byan ion implantation method.

Another embodiment of the present invention is a method formanufacturing a semiconductor device in which the oxide semiconductorcontains at least one selected from indium, zinc, and an element M (anelement M is aluminum, gallium, yttrium, or tin).

A transistor with stable electrical characteristics can be provided. Atransistor having normally-off electrical characteristics can beprovided. A transistor having a small subthreshold swing value can beprovided. A transistor having a small short-channel effect can beprovided. A transistor having a low leakage current in an off state canbe provided. A transistor having excellent electrical characteristicscan be provided. A transistor having high reliability can be provided. Atransistor with high frequency characteristics can be provided.

A semiconductor device including any of the transistors can be provided.A module including the semiconductor devices can be provided. Anelectronic device including the semiconductor device or the module canbe provided. A novel semiconductor device can be provided. A novelmodule can be provided. A novel electronic device can be provided.

Note that the description of these effects does not disturb theexistence of other effects. One embodiment of the present invention doesnot necessarily have all the effects listed above. Other effects will beapparent from and can be derived from the description of thespecification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A and 1B are a top view and a cross-sectional view illustrating atransistor of one embodiment of the present invention;

FIGS. 2A and 2B are a top view and a cross-sectional view illustrating amethod for manufacturing a transistor of one embodiment of the presentinvention;

FIGS. 3A and 3B are a top view and a cross-sectional view illustrating amethod for manufacturing a transistor of one embodiment of the presentinvention;

FIGS. 4A and 4B are a top view and a cross-sectional view illustrating amethod for manufacturing a transistor of one embodiment of the presentinvention;

FIGS. 5A and 5B are a top view and a cross-sectional view illustrating amethod for manufacturing a transistor of one embodiment of the presentinvention;

FIGS. 6A and 6B are a top view and a cross-sectional view illustrating amethod for manufacturing a transistor of one embodiment of the presentinvention;

FIGS. 7A to 7C are cross-sectional views each illustrating a transistorof one embodiment of the present invention;

FIGS. 8A to 8C are cross-sectional views each illustrating a transistorof one embodiment of the present invention;

FIG. 9 is a band diagram illustrating one embodiment of the presentinvention;

FIGS. 10A to 10D are Cs-corrected high-resolution TEM images of a crosssection of a CAAC-OS and a cross-sectional schematic view of a CAAC-OS;

FIGS. 11A to 11D are Cs-corrected high-resolution TEM images of a planeof a CAAC-OS;

FIGS. 12A to 12C show structural analysis of a CAAC-OS and a singlecrystal oxide semiconductor by XRD;

FIGS. 13A and 13B show electron diffraction patterns of a CAAC-OS;

FIG. 14 shows a change in crystal part of an In—Ga—Zn oxide induced byelectron irradiation;

FIGS. 15A and 15B are a top view and a cross-sectional view illustratinga method for manufacturing a transistor of one embodiment of the presentinvention;

FIGS. 16A and 16B are a top view and a cross-sectional view illustratinga method for manufacturing a transistor of one embodiment of the presentinvention;

FIGS. 17A and 17B are a top view and a cross-sectional view illustratinga method for manufacturing a transistor of one embodiment of the presentinvention;

FIGS. 18A and 18B are a top view and cross-sectional views illustratinga method for manufacturing a transistor of one embodiment of the presentinvention;

FIGS. 19A and 19B are a top view and a cross-sectional view illustratinga method for manufacturing a transistor of one embodiment of the presentinvention;

FIGS. 20A and 20B are a top view and a cross-sectional view illustratinga method for manufacturing a transistor of one embodiment of the presentinvention;

FIGS. 21A and 21B are a top view and a cross-sectional view illustratinga method for manufacturing a transistor of one embodiment of the presentinvention;

FIGS. 22A to 22C are cross-sectional views each illustrating atransistor of one embodiment of the present invention;

FIGS. 23A to 23C are cross-sectional views each illustrating atransistor of one embodiment of the present invention;

FIGS. 24A and 24B are circuit diagrams each illustrating a semiconductordevice of one embodiment of the present invention;

FIG. 25 is a cross-sectional view illustrating a semiconductor device ofone embodiment of the present invention;

FIG. 26 is a cross-sectional view illustrating a semiconductor device ofone embodiment of the present invention;

FIG. 27 is a cross-sectional view illustrating a semiconductor device ofone embodiment of the present invention;

FIGS. 28A and 28B are circuit diagrams each illustrating a memory deviceof one embodiment of the present invention;

FIG. 29 is a cross-sectional view illustrating a semiconductor device ofone embodiment of the present invention;

FIG. 30 is a cross-sectional view illustrating a semiconductor device ofone embodiment of the present invention;

FIG. 31 is a cross-sectional view illustrating a semiconductor device ofone embodiment of the present invention;

FIGS. 32A and 32B are plan views each illustrating a semiconductordevice of one embodiment of the present invention;

FIGS. 33A and 33B are block diagrams each illustrating a semiconductordevice of one embodiment of the present invention;

FIGS. 34A and 34B are cross-sectional views each illustrating asemiconductor device of one embodiment of the present invention;

FIGS. 35A and 35B are cross-sectional views each illustrating asemiconductor device of one embodiment of the present invention;

FIGS. 36A1 to 36A3 and 36B1 to 36B3 are perspective views andcross-sectional views illustrating semiconductor devices of oneembodiment of the present invention;

FIG. 37 is a block diagram illustrating a semiconductor device of oneembodiment of the present invention;

FIG. 38 is a circuit diagram illustrating a semiconductor device of oneembodiment of the present invention;

FIGS. 39A to 39C are a circuit diagram, a top view, and across-sectional view illustrating a semiconductor device of oneembodiment of the present invention;

FIGS. 40A and 40B are a circuit diagram and a cross-sectional viewillustrating a semiconductor device of one embodiment of the presentinvention;

FIGS. 41A to 41F are perspective views each illustrating an electronicdevice of one embodiment of the present invention;

FIG. 42 is a graph showing the amount of added fluorine in the depthdirection;

FIG. 43 is a graph showing sheet resistance values of samples; and

FIGS. 44A and 44B are graphs showing results of ESR measurement ofsamples.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments and examples of the present invention will bedescribed in detail with the reference to the drawings. However, thepresent invention is not limited to the description below, and it iseasily understood by those skilled in the art that modes and detailsdisclosed herein can be modified in various ways. Further, the presentinvention is not construed as being limited to description of theembodiments and the examples. In describing structures of the presentinvention with reference to the drawings, common reference numerals areused for the same portions in different drawings. Note that the samehatched pattern is applied to similar parts, and the similar parts arenot especially denoted by reference numerals in some cases.

Note that the size, the thickness of films (layers), or regions indrawings is sometimes exaggerated for simplicity.

In this specification and the like, the terms “film” and “layer” can beinterchanged with each other.

A voltage usually refers to a potential difference between a givenpotential and a reference potential (e.g., a source potential or aground potential (GND)). A voltage can be referred to as a potential andvice versa. Note that in general, a potential (a voltage) is relativeand is determined depending on the amount relative to a certainpotential. Therefore, a potential that is represented as a “groundpotential” or the like is not always 0 V. For example, the lowestpotential in a circuit may be represented as a “ground potential”.Alternatively, a substantially intermediate potential in a circuit maybe represented as a “ground potential”. In these cases, a positivepotential and a negative potential are set using the potential as areference.

Note that the ordinal numbers such as “first” and “second” are used forconvenience and do not denote the order of steps or the stacking orderof layers. Therefore, for example, the term “first” can be replaced withthe term “second”, “third”, or the like as appropriate. In addition, theordinal numbers in this specification and the like do not correspond tothe ordinal numbers which specify one embodiment of the presentinvention in some cases.

Note that a “semiconductor” has characteristics of an “insulator” insome cases when the conductivity is sufficiently low, for example.Further, a “semiconductor” and an “insulator” cannot be strictlydistinguished from each other in some cases because a bordertherebetween is not clear. Accordingly, a “semiconductor” in thisspecification can be called an “insulator” in some cases. Similarly, an“insulator” in this specification can be called a “semiconductor” insome cases.

Further, a “semiconductor” has characteristics of a “conductor” in somecases when the conductivity is sufficiently high, for example. Further,a “semiconductor” and a “conductor” cannot be strictly distinguishedfrom each other in some cases because a border therebetween is notclear. Accordingly, a “semiconductor” in this specification can becalled a “conductor” in some cases. Similarly, a “conductor” in thisspecification can be called a “semiconductor” in some cases.

Note that impurities in a semiconductor refer to, for example, elementsother than the main components of the semiconductor. For example, anelement with a concentration of lower than 0.1 atomic % is an impurity.When an impurity is contained, the density of states (DOS) may be formedin a semiconductor, the carrier mobility may be decreased, or thecrystallinity may be decreased. In the case where the semiconductor isan oxide semiconductor, examples of an impurity which changescharacteristics of the semiconductor include Group 1 elements, Group 2elements, Group 14 elements, Group 15 elements, and transition metalsother than the main components; specifically, there are hydrogen(included in water), lithium, sodium, silicon, boron, phosphorus,carbon, and nitrogen, for example. In the case of an oxidesemiconductor, oxygen vacancies may be formed by entry of impuritiessuch as hydrogen. In the case where the semiconductor is silicon,examples of an impurity which changes characteristics of thesemiconductor include oxygen, Group 1 elements except hydrogen, Group 2elements, Group 13 elements, and Group 15 elements.

Note that the channel length refers to, for example, the distancebetween a source (a source region or a source electrode) and a drain (adrain region or a drain electrode) in a region where a semiconductor (ora portion where a current flows in a semiconductor when a transistor ison) and a gate electrode overlap with each other or a region where achannel is formed in a plan view of the transistor. In one transistor,channel lengths in all regions are not necessarily the same. In otherwords, the channel length of one transistor is not limited to one valuein some cases. Therefore, in this specification, the channel length isany one of values, the maximum value, the minimum value, or the averagevalue in a region where a channel is formed.

The channel width refers to, for example, the length of a portion wherea source and a drain face each other in a region where a semiconductor(or a portion where a current flows in a semiconductor when a transistoris on) and a gate electrode overlap with each other, or a region where achannel is formed. In one transistor, channel widths in all regions arenot necessarily the same. In other words, the channel width of onetransistor is not limited to one value in some cases. Therefore, in thisspecification, the channel width is any one of values, the maximumvalue, the minimum value, or the average value in a region where achannel is formed.

Note that depending on transistor structures, a channel width in aregion where a channel is formed actually (hereinafter referred to as aneffective channel width) is different from a channel width shown in aplan view of a transistor (hereinafter referred to as an apparentchannel width) in some cases. For example, in a transistor having athree-dimensional structure, an effective channel width is greater thanan apparent channel width shown in a plan view of the transistor, andits influence cannot be ignored in some cases. For example, in aminiaturized transistor having a three-dimensional structure, theproportion of a channel formation region formed in a side surface of asemiconductor is high in some cases. In that case, an effective channelwidth obtained when a channel is actually formed is greater than anapparent channel width shown in the plan view.

In a transistor having a three-dimensional structure, an effectivechannel width is difficult to measure in some cases. For example, toestimate an effective channel width from a design value, it is necessaryto assume that the shape of a semiconductor is known as an assumptioncondition. Therefore, in the case where the shape of a semiconductor isnot known accurately, it is difficult to measure an effective channelwidth accurately.

Therefore, in this specification, in a plan view of a transistor, anapparent channel width that is a length of a portion where a source anda drain face each other in a region where a semiconductor and a gateelectrode overlap with each other is referred to as a surrounded channelwidth (SCW) in some cases. Further, in this specification, in the casewhere the term “channel width” is simply used, it may denote asurrounded channel width and an apparent channel width. Alternatively,in this specification, in the case where the term “channel width” issimply used, it may denote an effective channel width in some cases.Note that the values of a channel length, a channel width, an effectivechannel width, an apparent channel width, a surrounded channel width,and the like can be determined by obtaining and analyzing across-sectional TEM image and the like.

Note that in the case where electric field mobility, a current value perchannel width, and the like of a transistor are obtained by calculation,a surrounded channel width may be used for the calculation. In thatcase, the values might be different from those calculated by using aneffective channel width.

Note that in this specification, the description “A has a shape suchthat an end portion extends beyond an end portion of B” may indicate,for example, the case where at least one of end portions of A ispositioned on an outer side than at least one of end portions of B in atop view or a cross-sectional view. Thus, the description “A has a shapesuch that an end portion extends beyond an end portion of B” can be readas the description “one end portion of A is positioned on an outer sidethan one end portion of B in a top view,” for example.

In this specification, the term “parallel” indicates that the angleformed between two straight lines is greater than or equal to −10° andless than or equal to 10°, and accordingly also includes the case wherethe angle is greater than or equal to −5° and less than or equal to 5°.A term “substantially parallel” indicates that the angle formed betweentwo straight lines is greater than or equal to −30° and less than orequal to 30°. The term “perpendicular” indicates that the angle formedbetween two straight lines is greater than or equal to 80° and less thanor equal to 100°, and accordingly also includes the case where the angleis greater than or equal to 85° and less than or equal to 95°. A term“substantially perpendicular” indicates that the angle formed betweentwo straight lines is greater than or equal to 60° and less than orequal to 120°.

In this specification, trigonal and rhombohedral crystal systems areincluded in a hexagonal crystal system.

In this specification, a term “semiconductor” can be referred to as an“oxide semiconductor”. As the semiconductor, a Group 14 semiconductorsuch as silicon or germanium; a compound semiconductor such as siliconcarbide, germanium silicide, gallium arsenide, indium phosphide, zincselenide, or cadmium sulfide; or an organic semiconductor can be used.

Embodiment 1

In this embodiment, an example of a transistor of one embodiment of thepresent invention will be described.

<Transistor 1>

FIGS. 1A and 1B illustrate a transistor of one embodiment of the presentinvention. FIG. 1A is a top view of a transistor 100, and FIG. 1B is across-sectional view taken along dashed-dotted lines A1-A2 and A3-A4 inFIG. 1A. The transistor 100 includes a substrate 400, a conductor 413,an insulator 402, a semiconductor 406 a, a semiconductor 406 b, asemiconductor 406 c, a conductor 416 a, a conductor 416 b, an insulator412, and a conductor 404.

The semiconductors 406 a, 406 b, or 406 c of the transistor 100 cancontain fluorine. All of the three layers may contain fluorine.Alternatively, any one or two of the three layers may contain fluorine.

In the case where a semiconductor of a transistor includes a pluralityof layers as described in this embodiment, a semiconductor including achannel formation region preferably contains fluorine. For example, inthe case where the semiconductor 406 b includes a channel formationregion, the semiconductor 406 b preferably contains fluorine.

The conductor 404 functions as a first gate electrode (also referred toas a front gate electrode) of the transistor 100. The conductor 413functions as a second gate electrode (also referred to as a back gateelectrode) of the transistor 100. The conductor 416 a and the conductor416 b function as a source electrode and a drain electrode of thetransistor 100. The insulator 412 functions as a gate insulator.

In this embodiment, the transistor 100 is a top-gate transistorincluding a back gate; however, the present invention is not limitedthereto. For example, a back gate is not necessarily provided.Alternatively, a bottom-gate structure may be employed. In this case,the conductor 413 functions as a front gate, and the conductor 404functions as a back gate. Alternatively, the conductor 404 is notnecessarily provided.

A method for manufacturing the transistor 100 illustrated in FIGS. 1Aand 1B is described with reference to FIGS. 2A and 2B, FIGS. 3A and 3B,FIGS. 4A and 4B, FIGS. 5A and 5B, and FIGS. 6A and 6B.

FIG. 2A, FIG. 3A, FIG. 4A, FIG. 5A, and FIG. 6A are top viewsillustrating a method for manufacturing the transistor 100 of oneembodiment of the present invention. FIG. 2B, FIG. 3B, FIG. 4B, FIG. 5B,and FIG. 6B are each a cross-sectional view taken along dashed-dottedlines A1-A2 and A3-A4 shown in the corresponding top view.

First, a substrate 400 is prepared.

As the substrate 400, an insulator substrate, a semiconductor substrate,or a conductor substrate may be used, for example. As the insulatorsubstrate, a glass substrate, a quartz substrate, a sapphire substrate,a stabilized zirconia substrate (e.g., an yttria-stabilized zirconiasubstrate), or a resin substrate is used, for example. As thesemiconductor substrate, a single material semiconductor substrate ofsilicon, germanium, or the like or a compound semiconductor substratemade of silicon carbide, silicon germanium, gallium arsenide, indiumphosphide, zinc oxide, gallium oxide, or the like is used, for example.A semiconductor substrate in which an insulator region is provided inthe above semiconductor substrate, e.g., a silicon on insulator (SOI)substrate or the like is used. As the conductor substrate, a graphitesubstrate, a metal substrate, an alloy substrate, a conductive resinsubstrate, or the like is used. A substrate including a metal nitride, asubstrate including a metal oxide, or the like is used. An insulatorsubstrate provided with a conductor or a semiconductor, a semiconductorsubstrate provided with a conductor or an insulator, a conductorsubstrate provided with a semiconductor or an insulator, or the like isused. Alternatively, any of these substrates over which an element isprovided may be used. As the element provided over the substrate, acapacitor, a resistor, a switching element, a light-emitting element, amemory element, or the like is used.

Alternatively, a flexible substrate may be used as the substrate 400. Asa method for providing the transistor over a flexible substrate, thereis a method in which the transistor is formed over a non-flexiblesubstrate and then the transistor is separated and transferred to thesubstrate 400 which is a flexible substrate. In that case, a separationlayer is preferably provided between the non-flexible substrate and thetransistor. As the substrate 400, a sheet containing a fiber, a film, ora foil may be used. The substrate 400 may have elasticity. The substrate400 may have a property of returning to its original shape when bendingor pulling is stopped. Alternatively, the substrate 400 may have aproperty of not returning to its original shape. The thickness of thesubstrate 400 is, for example, greater than or equal to 5 μm and lessthan or equal to 1000 μm, preferably greater than or equal to 10 μm andless than or equal to 700 μm, or further preferably greater than orequal to 15 μm and less than or equal to 500 μm. When the substrate 400has a small thickness, the weight of the semiconductor device can bereduced. When the substrate 400 has a small thickness, even in the caseof using glass or the like, the substrate 400 may have elasticity or aproperty of returning to its original shape when bending or pulling isstopped. Therefore, an impact applied to the semiconductor device overthe substrate 400, which is caused by dropping or the like, can bereduced. That is, a durable semiconductor device can be provided.

For the substrate 400 which is a flexible substrate, metal, an alloy,resin, glass, or fiber thereof can be used, for example. The flexiblesubstrate 400 preferably has a lower coefficient of linear expansionbecause deformation due to an environment is suppressed. The flexiblesubstrate 400 is formed using, for example, a material whose coefficientof linear expansion is lower than or equal to 1×10⁻³/K, lower than orequal to 5×10⁻⁵/K, or lower than or equal to 1×10⁻⁵/K. Examples of theresin include polyester, polyolefin, polyamide (e.g., nylon or aramid),polyimide, polycarbonate, and acrylic. In particular, aramid ispreferably used for the flexible substrate 400 because of its lowcoefficient of linear expansion.

Next, a conductor is formed. The conductor may be formed by a sputteringmethod, a chemical vapor deposition (CVD) method, a molecular beamepitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomiclayer deposition (ALD) method, or the like.

CVD methods can be classified into a plasma enhanced CVD (PECVD) methodusing plasma, a thermal CVD (TCVD) method using heat, a photo CVD methodusing light, and the like. Moreover, the CVD method can include a metalCVD (MCVD) method and a metal organic CVD (MOCVD) method depending on asource gas.

In the case of a PECVD method, a high quality film can be obtained atrelatively low temperature. A TCVD method is a film formation method inwhich an object is not damaged by plasma because plasma is not used. Forexample, a wiring, an electrode, an element (e.g., transistor orcapacitor), or the like included in a semiconductor device might becharged up by receiving charges from plasma. In that case, accumulatedcharges might break the wiring, electrode, element, or the like includedin the semiconductor device. Such plasma damage is not caused in thecase of using a TCVD method, and thus the yield of a semiconductordevice can be increased. In addition, since plasma damage does not occurin the deposition by a TCVD method, a film with few defects is easilyobtained.

An ALD method also causes less plasma damage to an object. An ALD methoddoes not cause plasma damage during deposition, so that a film with fewdefects is easily obtained.

Unlike in a deposition method in which particles ejected from a targetor the like are deposited, in a CVD method and an ALD method, a film isformed by reaction at a surface of an object. Thus, a CVD method and anALD method enable favorable step coverage almost regardless of the shapeof an object. In particular, an ALD method enables excellent stepcoverage and excellent thickness uniformity and can be favorably usedfor covering a surface of an opening portion with a high aspect ratio,for example. On the other hand, an ALD method has a relatively lowdeposition rate; thus, it is sometimes preferable to combine an ALDmethod with another deposition method with a high deposition rate suchas a CVD method.

When a CVD method or an ALD method is used, composition of a film to beformed can be controlled with a flow rate ratio of the source gases. Forexample, by the CVD method or the ALD method, a film with a desiredcomposition can be formed by adjusting the flow ratio of a source gas.Moreover, with a CVD method or an ALD method, by changing the flow rateratio of the source gases while forming the film, a film whosecomposition is continuously changed can be formed. In the case where thefilm is formed while changing the flow rate ratio of the source gases,as compared to the case where the film is formed using a plurality ofdeposition chambers, time taken for the deposition can be reducedbecause time taken for transfer and pressure adjustment is omitted.Thus, semiconductor devices can be manufactured with improvedproductivity.

Next, a resist or the like is formed over the conductor and processingis performed using the resist, whereby a conductor 413 is formed. Notethat the case where the resist is simply formed also includes the casewhere a BARC is formed below the resist.

The resist is removed after the object is processed by etching or thelike. For the removal of the resist, plasma treatment and/or wet etchingare/is used. Note that as the plasma treatment, plasma ashing ispreferable. In the case where the removal of the resist or the like isnot enough, the remaining resist or the like may be removed using ozonewater and/or hydrofluoric acid at a concentration higher than or equalto 0.001 volume % and lower than or equal to 1 volume %, and the like.

The conductor to be the conductor 413 may be formed to have asingle-layer structure or a stacked-layer structure using a conductorcontaining, for example, one or more of boron, nitrogen, oxygen,fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese,cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum,ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or acompound of the above element may be used, for example, and a conductorcontaining aluminum, a conductor containing copper and titanium, aconductor containing copper and manganese, a conductor containingindium, tin, and oxygen, a conductor containing titanium and nitrogen,or the like may be used.

Then, an insulator 402 is formed (see FIGS. 2A and 2B). The insulator402 can be formed by a sputtering method, a CVD method, an MBE method, aPLD method, an ALD method, or the like.

The insulator 402 may be formed to have a single-layer structure or astacked-layer structure including an insulator containing, for example,boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon,phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium,lanthanum, neodymium, hafnium, or tantalum. The insulator 402 may beformed using aluminum oxide, magnesium oxide, silicon oxide, siliconoxynitride, silicon nitride oxide, silicon nitride, gallium oxide,germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide,neodymium oxide, hafnium oxide, or tantalum oxide.

The insulator 402 preferably includes excess oxygen and/or a hydrogentrap.

Here, an insulator including excess oxygen may release oxygen, theamount of which is higher than or equal to 1×10¹⁸ atoms/cm³, higher thanor equal to 1×10¹⁹ atoms/cm³, or higher than or equal to 1×10²⁰atoms/cm³ (converted into the number of oxygen atoms) in thermaldesorption spectroscopy (TDS) analysis in the range of a film surfacetemperature of 100° C. to 700° C. or 100° C. to 500° C.

The method of measuring the amount of released oxygen using TDS analysisis described below.

The total amount of released gas from a measurement sample in TDSanalysis is proportional to the integral value of the ion intensity ofthe released gas. Then, comparison with a reference sample is made,whereby the total amount of released gas can be calculated.

For example, the number of released oxygen molecules (N_(O2)) from ameasurement sample can be calculated according to the following formulausing the TDS results of a silicon substrate containing hydrogen at apredetermined density, which is a reference sample, and the TDS resultsof the measurement sample. Here, all gases having a mass-to-charge ratioof 32 which are obtained in the TDS analysis are assumed to originatefrom an oxygen molecule. Note that CH₃OH, which is a gas having themass-to-charge ratio of 32, is not taken into consideration because itis unlikely to be present. Furthermore, an oxygen molecule including anoxygen atom having a mass number of 17 or 18 which is an isotope of anoxygen atom is also not taken into consideration because the proportionof such a molecule in the natural world is minimal.

N_(O2)═N_(H2)/S_(H2)×S_(O2)×α

The value N_(H2) is obtained by conversion of the number of hydrogenmolecules desorbed from the reference sample into densities. The valueS_(H2) is the integral value of ion intensity in the case where thereference sample is subjected to the TDS analysis. Here, the referencevalue of the reference sample is set to N_(H2)/S_(H2). The value S_(O2)is the integral value of ion intensity when the measurement sample isanalyzed by TDS. The value α is a coefficient affecting the ionintensity in the TDS analysis. Refer to Japanese Published PatentApplication No. H6-275697 for details of the above formula. The amountof released oxygen was measured with a thermal desorption spectroscopyapparatus produced by ESCO Ltd., EMD-WA1000S/W using a silicon substratecontaining a certain amount of hydrogen atoms as the reference sample.

Furthermore, in the TDS analysis, oxygen is partly detected as an oxygenatom. The ratio between oxygen molecules and oxygen atoms can becalculated from the ionization rate of the oxygen molecules. Note that,since the above a includes the ionization rate of the oxygen molecules,the number of the released oxygen atoms can also be estimated throughthe evaluation of the number of the released oxygen molecules.

Note that N_(O2) is the number of the released oxygen molecules. Thenumber of released oxygen in the case of being converted into oxygenatoms is twice the number of the released oxygen molecules.

Furthermore, the insulator from which oxygen is released by heattreatment may contain a peroxide radical. Specifically, the spin densityof a signal attributed to the peroxide radical is greater than or equalto 5×10¹⁷ spins/cm³. Note that the insulator containing a peroxideradical may have an asymmetric signal with a g factor of approximately2.01 in electron spin resonance (ESR).

The insulator 402 may have a function of preventing diffusion ofimpurities from the substrate 400 and the like.

Next, a semiconductor to be the semiconductor 406 a is formed. Thesemiconductor to be the semiconductor 406 a can be formed by asputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like.

Next, oxygen may be added so that a semiconductor to be thesemiconductor 406 a contains excess oxygen. The addition of oxygen maybe performed by an ion implantation method at an acceleration voltage ofgreater than or equal to 2 kV and less than or equal to 10 kV at a doseof greater than or equal to 5×10¹⁴ ions/cm² and less than or equal to1×10¹⁷ ions/cm², for example.

Then, fluorine may be added to the semiconductor to be the semiconductor406 a. Note that the addition of oxygen to the semiconductor to be thesemiconductor 406 a and the addition of fluorine to the semiconductor tobe the semiconductor 406 a may be performed in reverse order.

The addition of fluorine may be performed by an ion implantation methodat an acceleration voltage of greater than or equal to 1 kV and lessthan or equal to 200 kV, preferably greater than or equal to 5 kV andless than or equal to 100 kV at a dose of greater than or equal to5×10¹⁹ ions/cm³ and less than or equal to 5×10²² ions/cm³, preferablygreater than or equal to 1×10²⁰ ions/cm³ and less than or equal to1×10²² ions/cm³, for example.

Next, a semiconductor to be the semiconductor 406 b is formed. Thesemiconductor to be the semiconductor 406 b can be formed by asputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like. Note that the semiconductor to be the semiconductor406 a and the semiconductor to be the semiconductor 406 b aresuccessively formed without being exposed to the air, in which caseimpurities can be prevented from entering the films and the interfacetherebetween.

Next, heat treatment is preferably performed. The heat treatment canreduce hydrogen concentration in the semiconductor to be thesemiconductor 406 a and in the semiconductor to be the semiconductor 406b in some cases. In addition, the heat treatment can reduce oxygenvacancies in the semiconductor to be the semiconductor 406 a and in thesemiconductor to be the semiconductor 406 b in some cases. The heattreatment may be performed at higher than or equal to 250° C. and lowerthan or equal to 650° C., preferably higher than or equal to 450° C. andlower than or equal to 600° C., more preferably higher than or equal to520° C. and lower than or equal to 570° C. The heat treatment isperformed in an inert gas atmosphere or an atmosphere containing anoxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heattreatment may be performed under a reduced pressure. Alternatively, theheat treatment may be performed in such a manner that heat treatment isperformed in an inert gas atmosphere, and then another heat treatment isperformed in an atmosphere containing an oxidizing gas at 10 ppm ormore, 1% or more, or 10% or more in order to fill desorbed oxygen. Bythe heat treatment, crystallinity of the semiconductor to be thesemiconductor 406 a and crystallinity of the semiconductor to be thesemiconductor 406 b can be increased and impurities such as hydrogen andwater can be removed.

Then, fluorine may be added to the semiconductor to be the semiconductor406 a and the semiconductor to be the semiconductor 406 b. Note that theheat treatment on the semiconductor to be the semiconductor 406 a andthe semiconductor to be the semiconductor 406 b and the addition offluorine to the semiconductor to be the semiconductor 406 a and thesemiconductor to be the semiconductor 406 b may be performed in reverseorder.

The addition of fluorine may be performed by an ion implantation methodat an acceleration voltage of greater than or equal to 1 kV and lessthan or equal to 200 kV, preferably greater than or equal to 5 kV andless than or equal to 100 kV at a dose of greater than or equal to5×10¹⁹ ions/cm³ and less than or equal to 5×10²² ions/cm³, preferablygreater than or equal to 1×10²⁰ ions/cm³ and less than or equal to1×10²² ions/cm³, for example.

Then, a resist or the like is formed over the semiconductor to be thesemiconductor 406 b and processing is performed using the resist,whereby the semiconductor 406 a and the semiconductor 406 b are formed(see FIGS. 3A and 3B).

Next, a conductor is formed. The conductor can be formed by a sputteringmethod, a CVD method, an MBE method, a PLD method, an ALD method, or thelike.

The conductor may be formed to have a single-layer structure or astacked-layer structure including a conductor containing, for example,one or more kinds of boron, nitrogen, oxygen, fluorine, silicon,phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel,copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium,silver, indium, tin, tantalum, and tungsten. An alloy or a compound ofthe above element may be used, for example, and a conductor containingaluminum, a conductor containing copper and titanium, a conductorcontaining copper and manganese, a conductor containing indium, tin, andoxygen, a conductor containing titanium and nitrogen, or the like may beused.

Next, a resist or the like is formed over the conductor, and theconductor is processed into a conductor 416 a and a conductor 416 busing the resist (see FIGS. 4A and 4B).

Then, fluorine may be added to the semiconductor 406 a and thesemiconductor 406 b. The addition of fluorine can be performed using theconductor 416 a and the conductor 416 b as masks. Accordingly, in thesemiconductors 406 a and 406 b, fluorine can be selectively added to aregion which does not overlap with the conductors 416 a and 416 b.

When the thicknesses of the conductors 416 a and 416 b are reduced, forexample, fluorine may also be added to regions overlapping with theconductors 416 a and 416 b in the semiconductors 406 a and 406 b.Accordingly, the semiconductors 406 a and 406 b in which regionsoverlapping with the conductors 416 a and 416 b and a region notoverlapping with the conductors 416 a and 416 b have different fluorineconcentrations can be formed. For example, in the semiconductors 406 aand 406 b, the fluorine concentration of the regions overlapping withthe conductors 416 a and 416 b is lower than that of the region notoverlapping with the conductors 416 a and 416 b.

The addition of fluorine may be performed by an ion implantation methodat an acceleration voltage of greater than or equal to 1 kV and lessthan or equal to 200 kV, preferably greater than or equal to 5 kV andless than or equal to 100 kV at a dose of greater than or equal to5×10¹⁹ ions/cm³ and less than or equal to 5×10²² ions/cm³, preferablygreater than or equal to 1×10²⁰ ions/cm³ and less than or equal to1×10²² ions/cm³, for example.

Here, for example, when the conductor 413, the insulator 402, theconductor 416 a, and the conductor 416 b serve as a gate electrode, agate insulator, a source electrode, and a drain electrode, respectively,a bottom-gate transistor may be obtained by completing the steps up toFIGS. 4A and 4B.

Next, a semiconductor 436 c is formed. The semiconductor 436 c can beformed by a sputtering method, a CVD method, an MBE method, a PLDmethod, an ALD method, or the like. Before the formation of thesemiconductor 436 c, surfaces of the semiconductor 406 a, thesemiconductor 406 b, the conductor 416 a, and the conductor 416 b may beetched. For example, plasma containing a rare gas can be used for theetching. After that, the semiconductor 436 c is successively formedwithout being exposed to the air, whereby impurities can be preventedfrom entering interfaces between the semiconductor 436 c and thesemiconductor 406 a, the semiconductor 406 b, the conductor 416 a, orthe conductor 416 b. In some cases, impurities at an interface betweenfilms are diffused more easily than impurities in a film. For thisreason, a reduction in impurity at the interfaces leads to stableelectrical characteristics of a transistor.

Then, fluorine may be added to the semiconductor 406 a, thesemiconductor 406 b, and the semiconductor 436 c. Note that fluorine isnot necessarily added to all of the semiconductors 406 a, 406 b, and 436c, and fluorine may be added to any one or two of these layers.

The addition of fluorine may be performed by an ion implantation methodat an acceleration voltage of greater than or equal to 1 kV and lessthan or equal to 200 kV, preferably greater than or equal to 5 kV andless than or equal to 100 kV at a dose of greater than or equal to5×10¹⁹ ions/cm³ and less than or equal to 5×10²² ions/cm³, preferablygreater than or equal to 1×10²⁰ ions/cm³ and less than or equal to1×10²² ions/cm³, for example.

Next, an insulator 442 is formed. The insulator 442 can be formed by asputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like. Note that the semiconductor 436 c and the insulator442 are successively formed without being exposed to the air, in whichcase impurities can be prevented from entering the films and theinterface therebetween.

The insulator 442 may have a single-layer structure or a stacked-layerstructure including an insulator containing, for example, boron, carbon,nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus,chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum,neodymium, hafnium, or tantalum. The insulator 442 may be formed usingaluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride,silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide,yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide,hafnium oxide, or tantalum oxide.

Then, fluorine may be added to the semiconductor 406 a, thesemiconductor 406 b, and the semiconductor 436 c through the insulator442. Note that fluorine is not necessarily added to all of thesemiconductors 406 a, 406 b, and 436 c, and fluorine may be added to anyone or two of these layers. In addition, fluorine may be added to theinsulator 442.

The addition of fluorine may be performed by an ion implantation methodat an acceleration voltage of greater than or equal to 1 kV and lessthan or equal to 200 kV, preferably greater than or equal to 5 kV andless than or equal to 100 kV at a dose of greater than or equal to5×10¹⁹ ions/cm³ and less than or equal to 5×10²² ions/cm³, preferablygreater than or equal to 1×10²⁰ ions/cm³ and less than or equal to1×10²² ions/cm³, for example.

Next, a conductor 434 is formed. The conductor 434 can be formed by asputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like. Note that the insulator 442 and the conductor 434are successively formed without being exposed to the air, in which caseimpurities can be prevented from entering the films and the interfacetherebetween (see FIGS. 5A and 5B).

The conductor 434 may be formed to have a single-layer structure or astacked-layer structure including a conductor containing, for example,one or more kinds of boron, nitrogen, oxygen, fluorine, silicon,phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel,copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium,silver, indium, tin, tantalum, and tungsten. An alloy or a compound ofthe above element may be used, for example, and a conductor containingaluminum, a conductor containing copper and titanium, a conductorcontaining copper and manganese, a conductor containing indium, tin, andoxygen, a conductor containing titanium and nitrogen, or the like may beused.

Then, a resist or the like is formed over the conductor 434 and theconductor 434 is processed into a conductor 404 using the resist. Theinsulator 442 is processed into an insulator 412 using the resist or theconductor 404. The semiconductor 436 c is processed into a semiconductor406 c using the resist, the conductor 404, or the insulator 412. Thesemiconductor 406 c, the insulator 412, and the conductor 404 have thesame shape when seen from the above, but a transistor of one embodimentof the present invention is not limited to this shape. For example, thesemiconductor 406 c, the insulator 412, and the conductor 404 may beprocessed using different resists. For example, after the insulator 412is formed, the conductor to be the conductor 404 may be formed; or afterthe conductor 404 is formed, a resist or the like may be formed over theinsulator to be the insulator 412. For example, the semiconductor 406 cmay be shared between adjacent transistors or the like (see FIGS. 6A and6B).

Next, an insulator may be formed. The insulator can be formed by asputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like.

The insulator may be formed to have a single-layer structure or astacked-layer structure including an insulator containing, for example,boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon,phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium,lanthanum, neodymium, hafnium, or tantalum. The insulator may be formedto have a single-layer structure or a stacked-layer structure includingan insulator containing, for example, aluminum oxide, silicon nitrideoxide, silicon nitride, gallium oxide, yttrium oxide, zirconium oxide,lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide.

The insulator preferably has a function of a barrier layer. Theinsulator has, for example, a function of blocking oxygen and/orhydrogen. Alternatively, the insulator preferably has a highercapability of blocking oxygen and/or hydrogen than the insulator 402 andthe insulator 412, for example.

Through the above process, the transistor 100 of one embodiment of thepresent invention can be manufactured.

As described above, fluorine is added to a channel formation region of asemiconductor, whereby oxygen vacancies in the semiconductor can befilled. Oxygen vacancies are filled with fluorine, which forms a stablebond, whereby a transistor having stable and favorable electricalcharacteristics can be provided.

As illustrated in FIG. 6B, the semiconductor 406 b can be electricallysurrounded by an electric field of the conductor 404 and the conductor413 (a structure in which a semiconductor is electrically surrounded byan electric field of a conductor is referred to as a surrounded channel(s-channel) structure). Therefore, a channel is formed in the entiresemiconductor 406 b (the top, bottom, and side surfaces). In thes-channel structure, a large amount of current can flow between a sourceand a drain of the transistor, so that a high on-state current can beachieved.

In the case where the transistor has the s-channel structure, a channelis formed also in the side surface of the semiconductor 406 b.Therefore, as the semiconductor 406 b has a larger thickness, thechannel formation region becomes larger. In other words, the thicker thesemiconductor 406 b is, the larger the on-state current of thetransistor is. In addition, when the semiconductor 406 b is thicker, theproportion of the region with a high carrier controllability increases,leading to a smaller subthreshold swing value. For example, thesemiconductor 406 b has a region with a thickness greater than or equalto 10 nm, preferably greater than or equal to 20 nm, further preferablygreater than or equal to 40 nm, still further preferably greater than orequal to 100 nm. In addition, to prevent a decrease in the productivityof the semiconductor device, the semiconductor 406 b has a region with athickness, for example, less than or equal to 300 nm, preferably lessthan or equal to 200 nm, further preferably less than or equal to 150nm.

The s-channel structure is suitable for a miniaturized transistorbecause a high on-state current can be achieved. A semiconductor deviceincluding the miniaturized transistor can have a high integration degreeand high density. For example, the transistor includes a region having achannel length of preferably less than or equal to 40 nm, furtherpreferably less than or equal to 30 nm, still further preferably lessthan or equal to 20 nm and a region having a channel width of preferablyless than or equal to 40 nm, further preferably less than or equal to 30nm, still further preferably less than or equal to 20 nm.

Note that the conductor 413 is not necessarily formed (see FIG. 7A).Furthermore, an edge of the insulator 412 and an edge of thesemiconductor 406 c may extend beyond an edge of the conductor 404 (seeFIG. 7B). The insulator 442 and the semiconductor 436 c are notnecessarily processed (see FIG. 7C). In the A1-A2 cross section, thewidth of the conductor 413 may be larger than that of the semiconductor406 b (see FIG. 8A). The conductor 413 may be in contact with theconductor 404 through an opening (see FIG. 8B). The conductor 404 is notnecessarily formed (see FIG. 8C).

<Semiconductor>

As described in this embodiment, by placing the semiconductor 406 a overthe semiconductor 406 b and placing the semiconductor 406 c under thesemiconductor 406 b, electrical characteristics of the transistor can beincreased in some cases.

The semiconductor 406 b is an oxide semiconductor containing indium, forexample. The oxide semiconductor 406 b can have high carrier mobility(electron mobility) by containing indium, for example. The semiconductor406 b preferably contains an element M. The element M is preferablyaluminum, gallium, yttrium, tin, or the like. Other elements which canbe used as the element M are boron, silicon, titanium, iron, nickel,germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium,tantalum, tungsten, and the like. Note that two or more of the aboveelements may be used in combination as the element M. The element M isan element having high bonding energy with oxygen, for example. Theelement M is an element whose bonding energy with oxygen is higher thanthat of indium. The element M is an element that can increase the energygap of the oxide semiconductor, for example. Furthermore, thesemiconductor 406 b preferably contains zinc. When the oxidesemiconductor contains zinc, the oxide semiconductor is easilycrystallized, in some cases.

Note that the semiconductor 406 b is not limited to the oxidesemiconductor containing indium. The semiconductor 406 b may be, forexample, an oxide semiconductor which does not contain indium andcontains zinc, an oxide semiconductor which does not contain indium andcontains gallium, or an oxide semiconductor which does not containindium and contains tin, e.g., a zinc tin oxide or a gallium tin oxide.

For the semiconductor 406 b, an oxide with a wide energy gap may beused, for example. For example, the energy gap of the semiconductor 406b is greater than or equal to 2.5 eV and less than or equal to 4.2 eV,preferably greater than or equal to 2.8 eV and less than or equal to 3.8eV, further preferably greater than or equal to 3 eV and less than orequal to 3.5 eV.

For example, the semiconductor 406 a and the semiconductor 406 c areoxide semiconductors including one or more elements, or two or moreelements other than oxygen included in the semiconductor 406 b. Sincethe semiconductor 406 a and the semiconductor 406 c each include one ormore elements, or two or more elements other than oxygen included in thesemiconductor 406 b, a defect state is less likely to be formed at theinterface between the semiconductor 406 a and the semiconductor 406 band the interface between the semiconductor 406 b and the semiconductor406 c.

The semiconductor 406 a, the semiconductor 406 b, and the semiconductor406 c preferably include at least indium. In the case of using anIn-M-Zn oxide as the semiconductor 406 a, when the summation of In and Mis assumed to be 100 atomic %, the proportions of In and M arepreferably set to be less than 50 atomic % and greater than 50 atomic %,respectively, further preferably less than 25 atomic % and greater than75 atomic %, respectively. In the case of using an In-M-Zn oxide as thesemiconductor 406 b, when the summation of In and M is assumed to be 100atomic %, the proportions of In and M are preferably set to be greaterthan 25 atomic % and less than 75 atomic %, respectively, furtherpreferably greater than 34 atomic % and less than 66 atomic %,respectively. In the case of using an In-M-Zn oxide as the semiconductor406 c, when the summation of In and M is assumed to be 100 atomic %, theproportions of In and M are preferably set to be less than 50 atomic %and greater than 50 atomic %, respectively, further preferably less than25 atomic % and greater than 75 atomic %, respectively. Note that thesemiconductor 406 c may be an oxide that is of the same type as theoxide of the semiconductor 406 a. Note that the semiconductor 406 aand/or the semiconductor 406 c do/does not necessarily contain indium insome cases. For example, the semiconductor 406 a and/or thesemiconductor 406 c may be gallium oxide. Note that the atomic ratios ofthe elements included in the semiconductor 406 a, the semiconductor 406b, and the semiconductor 406 c are not necessarily simple ratios ofintegers.

As the semiconductor 406 b, an oxide having an electron affinity higherthan those of the semiconductors 406 a and 406 c is used. For example,as the semiconductor 406 b, an oxide having an electron affinity higherthan those of the semiconductors 406 a and 406 c by 0.07 eV or higherand 1.3 eV or lower, preferably 0.1 eV or higher and 0.7 eV or lower,further preferably 0.15 eV or higher and 0.4 eV or lower is used. Notethat the electron affinity refers to an energy difference between thevacuum level and the bottom of the conduction band.

An indium gallium oxide has small electron affinity and a highoxygen-blocking property. Therefore, the semiconductor 406 c preferablyincludes an indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)]is, for example, higher than or equal to 70%, preferably higher than orequal to 80%, further preferably higher than or equal to 90%.

In the transistor in which the semiconductor 406 a and the semiconductor406 c are placed over and under the semiconductor 406 b as describedabove, when a gate voltage is applied, a channel is formed in thesemiconductor 406 b having the highest electron affinity in thesemiconductors 406 a, 406 b, and 406 c.

Here, in some cases, there is a mixed region of the semiconductor 406 aand the semiconductor 406 b between the semiconductor 406 a and thesemiconductor 406 b. Furthermore, in some cases, there is a mixed regionof the semiconductor 406 b and the semiconductor 406 c between thesemiconductor 406 b and the semiconductor 406 c. The mixed region has alow density of defect states. For that reason, the stack including thesemiconductor 406 a, the semiconductor 406 b, and the semiconductor 406c has a band structure where energy is changed continuously at eachinterface and in the vicinity of the interface (continuous junction)(see FIG. 9). Note that boundaries of the semiconductor 406 a, thesemiconductor 406 b, and the semiconductor 406 c are not clear in somecases.

At this time, electrons move mainly in the semiconductor 406 b, not inthe semiconductor 406 a and the semiconductor 406 c. As described above,when the density of defect states at the interface between thesemiconductor 406 a and the semiconductor 406 b and the density ofdefect states at the interface between the semiconductor 406 b and thesemiconductor 406 c are decreased, electron movement in thesemiconductor 406 b is less likely to be inhibited and the on-satecurrent of the transistor can be increased.

As factors of inhibiting electron movement are decreased, the on-statecurrent of the transistor can be increased. For example, in the casewhere there is no factor of inhibiting electron movement, electrons areassumed to be efficiently moved. Electron movement is inhibited, forexample, in the case where physical unevenness of the channel formationregion is large.

To increase the on-state current of the transistor, for example, rootmean square (RMS) roughness with a measurement area of 1 μm×1 μm of atop surface or a bottom surface (a formation surface; here, thesemiconductor 406 a) of the semiconductor 406 b is less than 1 nm,preferably less than 0.6 nm, further preferably less than 0.5 nm, stillfurther preferably less than 0.4 nm. The average surface roughness (alsoreferred to as Ra) with the measurement area of 1 μm×1 μm is less than 1nm, preferably less than 0.6 nm, further preferably less than 0.5 nm,still further preferably less than 0.4 nm. The maximum difference (P−V)with the measurement area of 1 μm×1 μm is less than 10 nm, preferablyless than 9 nm, further preferably less than 8 nm, still furtherpreferably less than 7 nm. RMS roughness, Ra, and P−V can be measuredusing a scanning probe microscope SPA-500 manufactured by SII NanoTechnology Inc.

Moreover, the thickness of the semiconductor 406 c is preferably assmall as possible to increase the on-state current of the transistor.For example, the semiconductor 406 c is formed to have a region with athickness of less than 10 nm, preferably less than or equal to 5 nm,further preferably less than or equal to 3 nm. Meanwhile, thesemiconductor 406 c has a function of blocking entry of elements otherthan oxygen (such as hydrogen and silicon) included in the adjacentinsulator into the semiconductor 406 b where a channel is formed. Forthis reason, it is preferable that the semiconductor 406 c have acertain thickness. For example, the semiconductor 406 c is formed tohave a region with a thickness of greater than or equal to 0.3 nm,preferably greater than or equal to 1 nm, further preferably greaterthan or equal to 2 nm. The semiconductor 406 c preferably has an oxygenblocking property to suppress outward diffusion of oxygen released fromthe insulator 402 and the like.

To improve reliability, preferably, the thickness of the semiconductor406 a is large and the thickness of the semiconductor 406 c is small.For example, the semiconductor 406 a has a region with a thickness of,for example, greater than or equal to 10 nm, preferably greater than orequal to 20 nm, further preferably greater than or equal to 40 nm, stillfurther preferably greater than or equal to 60 nm. When the thickness ofthe semiconductor 406 a is made large, a distance from an interfacebetween the adjacent insulator and the semiconductor 406 a to thesemiconductor 406 b in which a channel is formed can be large. Since theproductivity of the semiconductor device might be decreased, thesemiconductor 406 a has a region with a thickness of, for example, lessthan or equal to 200 nm, preferably less than or equal to 120 nm,further preferably less than or equal to 80 nm.

For example, a region with a silicon concentration measured by secondaryion mass spectrometry (SIMS) of higher than or equal to 1×10¹⁶ atoms/cm³and lower than or equal to 1×10¹⁹ atoms/cm³, preferably higher than orequal to 1×10¹⁶ atoms/cm³ and lower than or equal to 5×10¹⁸ atoms/cm³,further preferably higher than or equal to 1×10¹⁶ atoms/cm³ and lowerthan or equal to 2×10¹⁸ atoms/cm³ is provided between the semiconductor406 b and the semiconductor 406 a. A region with a silicon concentrationmeasured by SIMS of higher than or equal to 1×10¹⁶ atoms/cm³ and lowerthan or equal to 1×10¹⁹ atoms/cm³, preferably higher than or equal to1×10¹⁶ atoms/cm³ and lower than or equal to 5×10¹⁸ atoms/cm³, furtherpreferably higher than or equal to 1×10¹⁶ atoms/cm³ and lower than orequal to 2×10¹⁸ atoms/cm³ is provided between the semiconductor 406 band the semiconductor 406 c.

It is preferable to reduce the hydrogen concentration in thesemiconductor 406 a and the semiconductor 406 c in order to reduce thehydrogen concentration in the semiconductor 406 b. The semiconductor 406a and the semiconductor 406 c each include a region with a hydrogenconcentration measured by SIMS of higher than or equal to 1×10¹⁶atoms/cm³ and lower than or equal to 2×10²⁰ atoms/cm³, preferably higherthan or equal to 1×10¹⁶ atoms/cm³ and lower than or equal to 5×10¹⁹atoms/cm³, further preferably higher than or equal to 1×10¹⁶ atoms/cm³and lower than or equal to 1×10¹⁹ atoms/cm³, or still further preferablyhigher than or equal to 1×10¹⁶ atoms/cm³ and lower than or equal to5×10¹⁸ atoms/cm³. It is preferable to reduce the nitrogen concentrationin the semiconductor 406 a and the semiconductor 406 c in order toreduce the nitrogen concentration in the semiconductor 406 b. Thesemiconductor 406 a and the semiconductor 406 c includes a region with anitrogen concentration measured by SIMS of higher than or equal to1×10¹⁵ atoms/cm³ and lower than or equal to 5×10¹⁹ atoms/cm³, preferablyhigher than or equal to 1×10¹⁵ atoms/cm³ and lower than or equal to5×10¹⁸ atoms/cm³, further preferably higher than or equal to 1×10¹⁵atoms/cm³ and lower than or equal to 1×10¹⁸ atoms/cm³, or still furtherpreferably higher than or equal to 1×10¹⁵ atoms/cm³ and lower than orequal to 5×10¹⁷ atoms/cm³.

The above three-layer structure is an example. For example, a two-layerstructure without the semiconductor 406 a or the semiconductor 406 c maybe employed. Alternatively, a four-layer structure in which any one ofthe semiconductors described as examples of the semiconductor 406 a, thesemiconductor 406 b, and the semiconductor 406 c is provided under orover the semiconductor 406 a or under or over the semiconductor 406 cmay be employed. An n-layer structure (n is an integer of 5 or more) inwhich one or more of the semiconductors described as examples of thesemiconductor 406 a, the semiconductor 406 b, and the semiconductor 406c is provided at two or more of the following positions: over thesemiconductor 406 a, under the semiconductor 406 a, over thesemiconductor 406 c, and under the semiconductor 406 c.

<Structure of Oxide Semiconductor>

A structure of an oxide semiconductor is described below.

An oxide semiconductor is classified into a single crystal oxidesemiconductor and a non-single-crystal oxide semiconductor. Examples ofthe non-single-crystal oxide semiconductor include a c-axis alignedcrystalline oxide semiconductor (CAAC-OS), a polycrystalline oxidesemiconductor, a microcrystalline oxide semiconductor, and an amorphousoxide semiconductor.

From another perspective, an oxide semiconductor is classified into anamorphous oxide semiconductor and a crystalline oxide semiconductor.Examples of a crystalline oxide semiconductor include a single crystaloxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor,and a microcrystalline oxide semiconductor.

First, a CAAC-OS is described. Note that a CAAC-OS can be referred to asan oxide semiconductor including c-axis aligned nanocrystals (CANC).

A CAAC-OS is one of oxide semiconductors having a plurality of c-axisaligned crystal parts (also referred to as pellets).

In a combined analysis image (also referred to as a high-resolution TEMimage) of a bright-field image and a diffraction pattern of a CAAC-OS,which is obtained using a transmission electron microscope (TEM), aplurality of pellets can be observed. However, in the high-resolutionTEM image, a boundary between pellets, that is, a grain boundary is notclearly observed. Thus, in the CAAC-OS, a reduction in electron mobilitydue to the grain boundary is less likely to occur.

A CAAC-OS observed with TEM is described below. FIG. 10A shows ahigh-resolution TEM image of a cross section of the CAAC-OS which isobserved from a direction substantially parallel to the sample surface.The high-resolution TEM image is obtained with a spherical aberrationcorrector function. The high-resolution TEM image obtained with aspherical aberration corrector function is particularly referred to as aCs-corrected high-resolution TEM image. The Cs-corrected high-resolutionTEM image can be obtained with, for example, an atomic resolutionanalytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 10B is an enlarged Cs-corrected high-resolution TEM image of aregion (1) in FIG. 10A. FIG. 10B shows that metal atoms are arranged ina layered manner in a pellet. Each metal atom layer has a configurationreflecting unevenness of a surface over which the CAAC-OS is formed(hereinafter, the surface is referred to as a formation surface) or atop surface of the CAAC-OS, and is arranged parallel to the formationsurface or the top surface of the CAAC-OS.

As shown in FIG. 10B, the CAAC-OS has a characteristic atomicarrangement. The characteristic atomic arrangement is denoted by anauxiliary line in FIG. 10C. FIGS. 10B and 10C prove that the size of apellet is approximately 1 nm to 3 nm, and the size of a space caused bytilt of the pellets is approximately 0.8 nm. Therefore, the pellet canalso be referred to as a nanocrystal (nc).

Here, according to the Cs-corrected high-resolution TEM images, theschematic arrangement of pellets 5100 of a CAAC-OS over a substrate 5120is illustrated by such a structure in which bricks or blocks are stacked(see FIG. 10D). The part in which the pellets are tilted as observed inFIG. 10C corresponds to a region 5161 shown in FIG. 10D.

FIG. 11A shows a Cs-corrected high-resolution TEM image of a plane ofthe CAAC-OS observed from a direction substantially perpendicular to thesample surface. FIGS. 11B, 11C, and 11D are enlarged Cs-correctedhigh-resolution TEM images of regions (1), (2), and (3) in FIG. 11A,respectively. FIGS. 11B, 11C, and 11D indicate that metal atoms arearranged in a triangular, quadrangular, or hexagonal configuration in apellet. However, there is no regularity of arrangement of metal atomsbetween different pellets.

Next, a CAAC-OS analyzed by X-ray diffraction (XRD) is described. Forexample, when the structure of a CAAC-OS including an InGaZnO₄ crystalis analyzed by an out-of-plane method, a peak appears at a diffractionangle (2θ) of around 31° as shown in FIG. 12A. This peak is derived fromthe (009) plane of the InGaZnO₄ crystal, which indicates that crystalsin the CAAC-OS have c-axis alignment, and that the c-axes are aligned ina direction substantially perpendicular to the formation surface or thetop surface of the CAAC-OS.

Note that in structural analysis of the CAAC-OS by an out-of-planemethod, another peak may appear when 2θ is around 36°, in addition tothe peak at 2θ of around 31°. The peak at 2θ of around 36° indicatesthat a crystal having no c-axis alignment is included in part of theCAAC-OS. It is preferable that in the CAAC-OS analyzed by anout-of-plane method, a peak appear when 2θ is around 31° and that a peaknot appear when 2θ is around 36°.

On the other hand, in structural analysis of the CAAC-OS by an in-planemethod in which an X-ray is incident on a sample in a directionsubstantially perpendicular to the c-axis, a peak appears when 2θ isaround 56°. This peak is attributed to the (110) plane of the InGaZnO₄crystal. In the case of the CAAC-OS, when analysis (φ scan) is performedwith 2θ fixed at around 56° and with the sample rotated using a normalvector of the sample surface as an axis (φ axis), as shown in FIG. 12B,a peak is not clearly observed. In contrast, in the case of a singlecrystal oxide semiconductor of InGaZnO₄, when φ scan is performed with2θ fixed at around 56°, as shown in FIG. 12C, six peaks which arederived from crystal planes equivalent to the (110) plane are observed.Accordingly, the structural analysis using XRD shows that the directionsof a-axes and b-axes are irregularly oriented in the CAAC-OS.

Next, a CAAC-OS analyzed by electron diffraction is described. Forexample, when an electron beam with a probe diameter of 300 nm isincident on a CAAC-OS including an InGaZnO₄ crystal in a directionparallel to the sample surface, a diffraction pattern (also referred toas a selected-area transmission electron diffraction pattern) shown inFIG. 13A can be obtained. In this diffraction pattern, spots derivedfrom the (009) plane of an InGaZnO₄ crystal are included. Thus, theelectron diffraction also indicates that pellets included in the CAAC-OShave c-axis alignment and that the c-axes are aligned in a directionsubstantially perpendicular to the formation surface or the top surfaceof the CAAC-OS. Meanwhile, FIG. 13B shows a diffraction pattern obtainedin such a manner that an electron beam with a probe diameter of 300 nmis incident on the same sample in a direction perpendicular to thesample surface. As shown in FIG. 13B, a ring-like diffraction pattern isobserved. Thus, the electron diffraction also indicates that the a-axesand b-axes of the pellets included in the CAAC-OS do not have regularalignment. The first ring in FIG. 13B is considered to be derived fromthe (010) plane, the (100) plane, and the like of the InGaZnO₄ crystal.The second ring in FIG. 13B is considered to be derived from the (110)plane and the like.

Moreover, the CAAC-OS is an oxide semiconductor having a low density ofdefect states. Defects in the oxide semiconductor are, for example, adefect due to impurities and oxygen vacancies. Therefore, the CAAC-OScan be regarded as an oxide semiconductor with a low impurityconcentration, or an oxide semiconductor having a small number of oxygenvacancies.

The impurity contained in the oxide semiconductor might serve as acarrier trap or serve as a carrier generation source. Furthermore,oxygen vacancies in the oxide semiconductor serve as carrier traps orserve as carrier generation sources when hydrogen is captured therein.

Note that the impurity means an element other than the main componentsof the oxide semiconductor, such as hydrogen, carbon, silicon, or atransition metal element. For example, an element (specifically, siliconor the like) having higher strength of bonding to oxygen than a metalelement included in an oxide semiconductor extracts oxygen from theoxide semiconductor, which results in disorder of the atomic arrangementand reduced crystallinity of the oxide semiconductor. A heavy metal suchas iron or nickel, argon, carbon dioxide, or the like has a large atomicradius (or molecular radius), and thus disturbs the atomic arrangementof the oxide semiconductor and decreases crystallinity.

An oxide semiconductor having a low density of defect states (a smallnumber of oxygen vacancies) can have a low carrier density. Such anoxide semiconductor is referred to as a highly purified intrinsic orsubstantially highly purified intrinsic oxide semiconductor. A CAAC-OShas a low impurity concentration and a low density of defect states.That is, a CAAC-OS is likely to be highly purified intrinsic orsubstantially highly purified intrinsic oxide semiconductor. Thus, atransistor including a CAAC-OS rarely has negative threshold voltage (israrely normally on). The highly purified intrinsic or substantiallyhighly purified intrinsic oxide semiconductor has few carrier traps. Anelectric charge trapped by the carrier traps in the oxide semiconductortakes a long time to be released. The trapped electric charge may behavelike a fixed electric charge. Thus, the transistor which includes theoxide semiconductor having a high impurity concentration and a highdensity of defect states might have unstable electrical characteristics.However, a transistor including a CAAC-OS has small variation inelectrical characteristics and high reliability.

Since the CAAC-OS has a low density of defect states, carriers generatedby light irradiation or the like are less likely to be trapped in defectstates. Therefore, in a transistor using the CAAC-OS, change inelectrical characteristics due to irradiation with visible light orultraviolet light is small.

<Microcrystalline Oxide Semiconductor>

Next, a microcrystalline oxide semiconductor is described.

A microcrystalline oxide semiconductor has a region in which a crystalpart is observed and a region in which a crystal part is not clearlyobserved in a high-resolution TEM image. In most cases, the size of acrystal part included in the microcrystalline oxide semiconductor isgreater than or equal to 1 nm and less than or equal to 100 nm, orgreater than or equal to 1 nm and less than or equal to 10 nm. An oxidesemiconductor including a nanocrystal (nc) that is a microcrystal with asize greater than or equal to 1 nm and less than or equal to 10 nm, or asize greater than or equal to 1 nm and less than or equal to 3 nm isspecifically referred to as a nanocrystalline oxide semiconductor(nc-OS). In a high-resolution TEM image of the nc-OS, for example, agrain boundary is not clearly observed in some cases. Note that there isa possibility that the origin of the nanocrystal is the same as that ofa pellet in a CAAC-OS. Therefore, a crystal part of the nc-OS may bereferred to as a pellet in the following description.

In the nc-OS, a microscopic region (for example, a region with a sizegreater than or equal to 1 nm and less than or equal to 10 nm, inparticular, a region with a size greater than or equal to 1 nm and lessthan or equal to 3 nm) has a periodic atomic arrangement. There is noregularity of crystal orientation between different pellets in thenc-OS. Thus, the orientation of the whole film is not ordered.Accordingly, the nc-OS cannot be distinguished from an amorphous oxidesemiconductor, depending on an analysis method. For example, when thenc-OS is subjected to structural analysis by an out-of-plane method withan XRD apparatus using an X-ray having a diameter larger than the sizeof a pellet, a peak which shows a crystal plane does not appear.Furthermore, a diffraction pattern like a halo pattern is observed whenthe nc-OS is subjected to electron diffraction using an electron beamwith a probe diameter (e.g., 50 nm or larger) that is larger than thesize of a pellet (the electron diffraction is also referred to asselected-area electron diffraction). Meanwhile, spots appear in ananobeam electron diffraction pattern of the nc-OS when an electron beamhaving a probe diameter close to or smaller than the size of a pellet isapplied. Moreover, in a nanobeam electron diffraction pattern of thenc-OS, regions with high luminance in a circular (ring) pattern areshown in some cases. Also in a nanobeam electron diffraction pattern ofthe nc-OS, a plurality of spots is shown in a ring-like region in somecases.

Since there is no regularity of crystal orientation between the pellets(nanocrystals) as mentioned above, the nc-OS can also be referred to asan oxide semiconductor including random aligned nanocrystals (RANC) oran oxide semiconductor including non-aligned nanocrystals (NANC).

The nc-OS is an oxide semiconductor that has high regularity as comparedwith an amorphous oxide semiconductor. Therefore, the nc-OS is likely tohave a lower density of defect states than an amorphous oxidesemiconductor. Note that there is no regularity of crystal orientationbetween different pellets in the nc-OS. Therefore, the nc-OS has ahigher density of defect states than the CAAC-OS.

<Amorphous Oxide Semiconductor>

Next, an amorphous oxide semiconductor is described.

The amorphous oxide semiconductor is an oxide semiconductor havingdisordered atomic arrangement and no crystal part and exemplified by anoxide semiconductor which exists in an amorphous state as quartz.

In a high-resolution TEM image of the amorphous oxide semiconductor,crystal parts cannot be found.

When the amorphous oxide semiconductor is subjected to structuralanalysis by an out-of-plane method with an XRD apparatus, a peak whichshows a crystal plane does not appear. A halo pattern is observed whenthe amorphous oxide semiconductor is subjected to electron diffraction.Furthermore, a spot is not observed and only a halo pattern appears whenthe amorphous oxide semiconductor is subjected to nanobeam electrondiffraction.

There are various understandings of an amorphous structure. For example,a structure whose atomic arrangement does not have ordering at all iscalled a completely amorphous structure. Meanwhile, a structure whichdoes not have long-range ordering but has ordering in a range from anatom to the nearest neighbor atoms or to the second-nearest neighboratoms is also called an amorphous structure. Therefore, the strictestdefinition does not permit an oxide semiconductor to be called anamorphous oxide semiconductor as long as even a negligible degree ofordering is present in an atomic arrangement. At least an oxidesemiconductor having long-term ordering cannot be called an amorphousoxide semiconductor. Accordingly, because of the presence of crystalpart, for example, a CAAC-OS and an nc-OS cannot be called an amorphousoxide semiconductor or a completely amorphous oxide semiconductor.

<Amorphous-Like Oxide Semiconductor>

Note that an oxide semiconductor may have a structure intermediatebetween the nc-OS and the amorphous oxide semiconductor. The oxidesemiconductor having such a structure is specifically referred to as anamorphous-like oxide semiconductor (a-like OS).

In a high-resolution TEM image of the a-like OS, a void may be observed.Furthermore, in the high-resolution TEM image, there are a region wherea crystal part is clearly observed and a region where a crystal part isnot observed.

The a-like OS has an unstable structure because it contains a void. Toverify that an a-like OS has an unstable structure as compared with aCAAC-OS and an nc-OS, a change in structure caused by electronirradiation is described below.

An a-like OS (referred to as Sample A), an nc-OS (referred to as SampleB), and a CAAC-OS (referred to as Sample C) are prepared as samplessubjected to electron irradiation. Each of the samples is an In—Ga—Znoxide.

First, a high-resolution cross-sectional TEM image of each sample isobtained. The high-resolution cross-sectional TEM images show that allthe samples have crystal parts.

Note that which part is regarded as a crystal part is determined asfollows. It is known that a unit cell of an InGaZnO₄ crystal has astructure in which nine layers including three In—O layers and sixGa—Zn—O layers are stacked in the c-axis direction. The distance betweenthe adjacent layers is equivalent to the lattice spacing on the (009)plane (also referred to as d value). The value is calculated to be 0.29nm from crystal structural analysis. Accordingly, a portion where thelattice spacing between lattice fringes is greater than or equal to 0.28nm and less than or equal to 0.30 nm is regarded as a crystal part ofInGaZnO₄. Each of lattice fringes corresponds to the a-b plane of theInGaZnO₄ crystal.

FIG. 14 shows change in the average size of crystal parts (at 22 pointsto 45 points) in each sample. Note that the crystal part sizecorresponds to the length of a lattice fringe. FIG. 14 indicates thatthe crystal part size in the a-like OS increases with an increase in thecumulative electron dose. Specifically, as shown by (1) in FIG. 14, acrystal part of approximately 1.2 nm (also referred to as an initialnucleus) at the start of TEM observation grows to a size ofapproximately 2.6 nm at a cumulative electron dose of 4.2×10⁸ e⁻/nm². Incontrast, the crystal part size in the nc-OS and the CAAC-OS showslittle change from the start of electron irradiation to a cumulativeelectron dose of 4.2×10⁸ e⁻/nm². Specifically, as shown by (2) and (3)in FIG. 14, the average crystal sizes in an nc-OS and a CAAC-OS areapproximately 1.4 nm and approximately 2.1 nm, respectively, regardlessof the cumulative electron dose.

In this manner, growth of the crystal part in the a-like OS is inducedby electron irradiation. In contrast, in the nc-OS and the CAAC-OS,growth of the crystal part is hardly induced by electron irradiation.Therefore, the a-like OS has an unstable structure as compared with thenc-OS and the CAAC-OS.

The a-like OS has a lower density than the nc-OS and the CAAC-OS becauseit contains a void. Specifically, the density of the a-like OS is higherthan or equal to 78.6% and lower than 92.3% of the density of the singlecrystal oxide semiconductor having the same composition. The density ofeach of the nc-OS and the CAAC-OS is higher than or equal to 92.3% andlower than 100% of the density of the single crystal oxide semiconductorhaving the same composition. Note that it is difficult to deposit anoxide semiconductor having a density of lower than 78% of the density ofthe single crystal oxide semiconductor.

For example, in the case of an oxide semiconductor having an atomicratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO₄ with arhombohedral crystal structure is 6.357 g/cm³. Accordingly, in the caseof the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, thedensity of the a-like OS is higher than or equal to 5.0 g/cm³ and lowerthan 5.9 g/cm³. For example, in the case of the oxide semiconductorhaving an atomic ratio of In:Ga:Zn=1:1:1, the density of each of thenc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm³ and lowerthan 6.3 g/cm³.

Note that there is a possibility that an oxide semiconductor having acertain composition cannot exist in a single crystal structure. In thatcase, single crystal oxide semiconductors with different compositionsare combined at an adequate ratio, which makes it possible to calculatedensity equivalent to that of a single crystal oxide semiconductor withthe desired composition. The density of a single crystal oxidesemiconductor having the desired composition can be calculated using aweighted average according to the combination ratio of the singlecrystal oxide semiconductors with different compositions. Note that itis preferable to use as few kinds of single crystal oxide semiconductorsas possible to calculate the density.

As described above, oxide semiconductors have various structures andvarious properties. Note that an oxide semiconductor may be a stackedlayer including two or more films of an amorphous oxide semiconductor,an a-like OS, a microcrystalline oxide semiconductor, and a CAAC-OS, forexample.

Embodiment 2

In this embodiment, a method for manufacturing a transistor whose shapeis partly different from that of the transistor in Embodiment 1 isdescribed.

<Transistor 2>

FIG. 15A, FIG. 16A, FIG. 17A, FIG. 18A, FIG. 19A, FIG. 20A, and FIG. 21Aare top views illustrating a method for manufacturing a transistor. FIG.15B, FIG. 16B, FIG. 17B, FIG. 18B, FIG. 19B, FIG. 20B, and FIG. 21B areeach a cross-sectional view taken along dashed dotted lines F1-F2 andF3-F4 shown in the corresponding top view.

First, a substrate 500 is prepared. For the substrate 500, thedescription of the substrate 400 is referred to.

Next, a conductor is formed. The conductor may be formed by a sputteringmethod, a CVD method, an MBE method, a PLD method, an ALD method, or thelike.

Next, a resist or the like is formed over the conductor and theconductor is processed into a conductor 513 using the resist.

Next, an insulator is formed. The insulator can be formed by asputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like.

Next, etching is performed from the top surface of the insulator towardthe bottom surface thereof such that the etched surface is parallel tothe bottom surface of the substrate 500 and the conductor 513 isexposed, whereby an insulator 503 is formed (see FIGS. 15A and 15B).When the insulator 503 is formed in this way, the top surface of theconductor 513 can be positioned at substantially the same level as thetop surface of the insulator 503. Therefore, a defect in shape in alater step can be inhibited.

Then, an insulator 502 is formed (see FIGS. 16A and 16B). The insulator502 can be formed by a sputtering method, a CVD method, an MBE method, aPLD method, an ALD method, or the like. For the insulator 502, thedescription of the insulator 402 is referred to.

Next, a semiconductor 536 a is formed. The semiconductor 536 a can beformed by a sputtering method, a CVD method, an MBE method, a PLDmethod, an ALD method, or the like. For the semiconductor 536 a, thedescription of the semiconductor to be the semiconductor 406 a isreferred to.

Next, oxygen may be added so that the semiconductor 536 a containsexcess oxygen. The addition of oxygen may be performed by an ionimplantation method at an acceleration voltage of greater than or equalto 2 kV and less than or equal to 10 kV at a dose of greater than orequal to 5×10¹⁴ ions/cm² and less than or equal to 1×10¹⁷ ions/cm², forexample.

Then, fluorine may be added to the semiconductor 536 a. Note that theaddition of oxygen to the semiconductor 536 a and the addition offluorine to the semiconductor 536 a may be performed in reverse order.

The addition of fluorine may be performed by an ion implantation methodat an acceleration voltage of greater than or equal to 1 kV and lessthan or equal to 200 kV, preferably greater than or equal to 5 kV andless than or equal to 100 kV at a dose of greater than or equal to5×10¹⁹ ions/cm³ and less than or equal to 5×10²² ions/cm³, preferablygreater than or equal to 1×10²⁰ ions/cm³ and less than or equal to1×10²² ions/cm³, for example.

Next, a semiconductor 536 b is formed. The semiconductor 536 b can beformed by a sputtering method, a CVD method, an MBE method, a PLDmethod, an ALD method, or the like. For the semiconductor 536 b, thedescription of the semiconductor to be the semiconductor 406 b isreferred to. Note that the semiconductor 536 a and the semiconductor 536b are successively formed without being exposed to the air, in whichcase impurities can be prevented from entering the films and theinterface therebetween.

Next, heat treatment is preferably performed. The heat treatment may beperformed at higher than or equal to 250° C. and lower than or equal to650° C., preferably higher than or equal to 450° C. and lower than orequal to 600° C., more preferably higher than or equal to 520° C. andlower than or equal to 570° C. The heat treatment is performed in aninert gas atmosphere or an atmosphere containing an oxidizing gas at 10ppm or more, 1% or more, or 10% or more. The heat treatment may beperformed under a reduced pressure. Alternatively, the heat treatmentmay be performed in such a manner that heat treatment is performed in aninert gas atmosphere, and then another heat treatment is performed in anatmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or10% or more in order to fill desorbed oxygen. By the heat treatment,crystallinity of the semiconductor 536 a and crystallinity of thesemiconductor 536 b can be increased and impurities such as hydrogen andwater can be removed.

Then, fluorine may be added to the semiconductor 536 a and thesemiconductor 536 b. Note that the heat treatment on the semiconductor536 a and the semiconductor 536 b and the addition of fluorine to thesemiconductor 536 a and the semiconductor 536 b may be performed inreverse order.

The addition of fluorine may be performed by an ion implantation methodat an acceleration voltage of greater than or equal to 1 kV and lessthan or equal to 200 kV, preferably greater than or equal to 5 kV andless than or equal to 100 kV at a dose of greater than or equal to5×10¹⁹ ions/cm³ and less than or equal to 5×10²² ions/cm³, preferablygreater than or equal to 1×10²⁰ ions/cm³ and less than or equal to1×10²² ions/cm³, for example.

Next, a conductor is formed. The conductor can be formed by a sputteringmethod, a CVD method, an MBE method, a PLD method, an ALD method, or thelike. The description of the conductor to be the conductor 416 a and theconductor 416 b is referred to for the conductor.

Next, a resist or the like is formed over the conductor, and theconductor is processed into a conductor 516 a and a conductor 516 busing the resist (see FIGS. 17A and 17B).

Then, fluorine may be added to the semiconductor 536 a and thesemiconductor 536 b. The addition of fluorine can be performed using theconductor 516 a and the conductor 516 b as masks. Accordingly, in thesemiconductors 536 a and 536 b, fluorine can be selectively added to aregion which does not overlap with the conductors 516 a and 516 b.

When the thicknesses of the conductors 516 a and 516 b are reduced, forexample, fluorine may also be added to regions overlapping with theconductors 516 a and 516 b in the semiconductors 536 a and 536 b.Accordingly, the semiconductors 536 a and 536 b in which regionsoverlapping with the conductors 516 a and 516 b and a region notoverlapping with the conductors 516 a and 516 b have different fluorineconcentrations can be formed. For example, in the semiconductors 536 aand 536 b, the fluorine concentration of the regions overlapping withthe conductors 516 a and 516 b is lower than that of the region notoverlapping with the conductors 516 a and 516 b.

The addition of fluorine may be performed by an ion implantation methodat an acceleration voltage of greater than or equal to 1 kV and lessthan or equal to 200 kV, preferably greater than or equal to 5 kV andless than or equal to 100 kV at a dose of greater than or equal to5×10¹⁹ ions/cm³ and less than or equal to 5×10²² ions/cm³, preferablygreater than or equal to 1×10²⁰ ions/cm³ and less than or equal to1×10²² ions/cm³, for example.

Then, a resist or the like is formed over the semiconductor 536 b andprocessing is performed using the resist, the conductor 516 a, and theconductor 516 b, whereby a semiconductor 506 a and a semiconductor 506 bare formed (see FIGS. 18A and 18B).

Note that the conductor 516 a, the conductor 516 b, the semiconductor506 a, and the semiconductor 506 b may be formed in the following mannerafter the formation of the conductor.

First, a resist or the like is formed over the conductor, and processingis performed using the resist, whereby the conductor 516, thesemiconductor 506 b, and the semiconductor 506 a are formed (see FIGS.21A and 21B). At this time, the semiconductor 506 a and thesemiconductor 506 b may be formed using the conductor 516 after theresist is removed.

Next, a resist or the like is formed over the conductor 516, and theconductor is processed into the conductor 516 a and the conductor 516 busing the resist (see FIGS. 18A and 18B).

Next, a semiconductor 536 c is formed. The semiconductor 536 c can beformed by a sputtering method, a CVD method, an MBE method, a PLDmethod, an ALD method, or the like. For the semiconductor 536 c, thedescription of the semiconductor 436 c is referred to.

Next, an insulator 542 is formed. The insulator 542 can be formed by asputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like. For the insulator 542, the description of theinsulator 442 is referred to.

Then, fluorine may be added to the semiconductor 506 a, thesemiconductor 506 b, and the semiconductor 536 c through the insulator542. Note that fluorine is not necessarily added to all of thesemiconductors 506 a, 506 b, and 536 c, and fluorine may be added to anyone or two of these layers. In addition, fluorine may be added to theinsulator 542.

The addition of fluorine may be performed by an ion implantation methodat an acceleration voltage of greater than or equal to 1 kV and lessthan or equal to 200 kV, preferably greater than or equal to 5 kV andless than or equal to 100 kV at a dose of greater than or equal to5×10¹⁹ ions/cm³ and less than or equal to 5×10²² ions/cm³, preferablygreater than or equal to 1×10²⁰ ions/cm³ and less than or equal to1×10²² ions/cm³, for example.

Next, a conductor 534 is formed (see FIGS. 19A and 19B). The conductor534 can be formed by a sputtering method, a CVD method, an MBE method, aPLD method, an ALD method, or the like. For the conductor 534, thedescription of the conductor 434 is referred to.

Then, a resist or the like is formed over the conductor 534 and theconductor 534 is processed into a conductor 504 using the resist. Theinsulator 542 is processed into an insulator 512 using the resist or theconductor 504. The semiconductor 536 c is processed into a semiconductor506 c using the resist, the conductor 504, or the insulator 542 (seeFIGS. 20A and 20B). Note that here, the semiconductor 506 c, theinsulator 512, and the conductor 504 have the same shape when seen fromthe above, but a transistor of one embodiment of the present inventionis not limited to this shape. For example, the insulator 512 and theconductor 504 may be processed using different resists. For example,after the insulator 512 is formed, the conductor to be the conductor 504may be formed; or after the conductor 504 is formed, a resist or thelike may be formed over the insulator to be the insulator 512. Forexample, the semiconductor 506 c may be shared between adjacenttransistors or the like.

Next, an insulator may be formed. The insulator can be formed by asputtering method, a CVD method, an MBE method, a PLD method, an ALDmethod, or the like.

The insulator may be formed to have a single-layer structure or astacked-layer structure including an insulator containing, for example,boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon,phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium,lanthanum, neodymium, hafnium, or tantalum. The insulator is preferablyformed to have a single-layer structure or a stacked-layer structureincluding an insulator containing, for example, aluminum oxide, siliconnitride oxide, silicon nitride, gallium oxide, yttrium oxide, zirconiumoxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalumoxide.

The insulator preferably has a function of a barrier layer. Theinsulator has, for example, a function of blocking oxygen and/orhydrogen. Alternatively, the insulator preferably has a highercapability of blocking oxygen and/or hydrogen than the insulator 502 andthe insulator 512, for example.

Through the above process, the transistor of one embodiment of thepresent invention can be manufactured.

As described above, fluorine is added to a channel formation region of asemiconductor, whereby oxygen vacancies in the semiconductor can befilled. Oxygen vacancies are filled with fluorine, which forms a stablebond, whereby a transistor having stable and favorable electricalcharacteristics can be provided.

As illustrated in FIG. 20B, the transistor has an s-channel structure.The electric field from the conductor 504 and the conductor 513 is lesslikely to be inhibited by the conductor 516 a, the conductor 516 b, andthe like at the side surface of the semiconductor 506 b.

Note that the conductor 513 is not necessarily formed (see FIG. 22A).Furthermore, an edge of the insulator 512 and an edge of thesemiconductor 506 c may extend beyond an edge of the conductor 504 (seeFIG. 22B). The insulator 542 and the semiconductor 536 c are notnecessarily processed (see FIG. 22C). In the F1-F2 cross section, thewidth of the conductor 513 may be larger than that of the semiconductor506 b (see FIG. 23A). The conductor 513 may be in contact with theconductor 504 through an opening (see FIG. 23B). The conductor 504 isnot necessarily formed (see FIG. 23C).

Embodiment 3

In this embodiment, an example of a circuit of a semiconductor deviceincluding a transistor or the like of one embodiment of the presentinvention is described.

<CMOS Inverter>

A circuit diagram in FIG. 24A illustrates a configuration of a so-calledCMOS inverter in which a p-channel transistor 2200 and an n-channeltransistor 2100 are connected to each other in series and gates of themare connected to each other. It is preferable that a transistorincluding an oxide semiconductor be used as the n-channel transistor2100. Thus, power consumption of the CMOS inverter circuit can bereduced.

<CMOS Analog Switch>

A circuit diagram in FIG. 24B illustrates a configuration in whichsources of the transistors 2100 and 2200 are connected to each other anddrains of the transistors 2100 and 2200 are connected to each other.With such a configuration, the transistors can function as a so-calledCMOS analog switch. It is preferable that a transistor including anoxide semiconductor be used as the n-channel transistor 2100.

<Structure 1 of Semiconductor Device>

FIG. 25 is a cross-sectional view of the semiconductor device of FIG.24A. The semiconductor device shown in FIG. 25 includes the transistor2200 and the transistor 2100. The transistor 2100 is placed above thetransistor 2200. Although an example where the transistor shown in FIGS.20A and 20B is used as the transistor 2100 is shown, a semiconductordevice of one embodiment of the present invention is not limitedthereto. For example, any of the transistors illustrated in FIGS. 6A and6B, FIGS. 7A to 7C, FIGS. 8A to 8C, FIGS. 22A to 22C, and FIGS. 23A to23C can be used as the transistor 2100. Therefore, the descriptionregarding the above-mentioned transistors is referred to for thetransistor 2100 as appropriate.

The transistor 2200 shown in FIG. 25 is a transistor using asemiconductor substrate 450. The transistor 2200 includes a region 472 ain the semiconductor substrate 450, a region 472 b in the semiconductorsubstrate 450, an insulator 462, and a conductor 454.

In the transistor 2200, the regions 472 a and 472 b have functions of asource region and a drain region. The insulator 462 has a function of agate insulator. The conductor 454 has a function of a gate electrode.Thus, the resistance of a channel formation region can be controlled bya potential applied to the conductor 454. In other words, conduction ornon-conduction between the region 472 a and the region 472 b can becontrolled by the potential applied to the conductor 454.

For the semiconductor substrate 450, a single-material semiconductorsubstrate of silicon, germanium, or the like or a compound semiconductorsubstrate made of silicon carbide, silicon germanium, gallium arsenide,indium phosphide, zinc oxide, gallium oxide, or the like may be used,for example. A single crystal silicon substrate is preferably used asthe semiconductor substrate 450.

For the semiconductor substrate 450, a semiconductor substrate includingimpurities imparting n-type conductivity is used. However, asemiconductor substrate including impurities imparting p-typeconductivity may be used as the semiconductor substrate 450. In thatcase, a well including impurities imparting the n-type conductivity maybe provided in a region where the transistor 2200 is formed.Alternatively, the semiconductor substrate 450 may be an i-typesemiconductor substrate.

A top surface of the semiconductor substrate 450 preferably has a (110)plane. Thus, on-state characteristics of the transistor 2200 can beimproved.

The regions 472 a and 472 b are regions including impurities impartingthe p-type conductivity. Accordingly, the transistor 2200 has astructure of a p-channel transistor.

Note that the transistor 2200 is apart from an adjacent transistor by aregion 460 and the like. The region 460 is an insulating region.

The semiconductor device shown in FIG. 25 includes an insulator 464, aninsulator 466, an insulator 468, a conductor 480 a, a conductor 480 b, aconductor 480 c, a conductor 478 a, a conductor 478 b, a conductor 478c, a conductor 476 a, a conductor 476 b, a conductor 474 a, a conductor474 b, a conductor 474 c, a conductor 496 a, a conductor 496 b, aconductor 496 c, a conductor 496 d, a conductor 498 a, a conductor 498b, a conductor 498 c, an insulator 490, an insulator 492, and aninsulator 494.

The insulator 464 is placed over the transistor 2200. The insulator 466is placed over the insulator 464. The insulator 468 is placed over theinsulator 466. The insulator 490 is placed over the insulator 468. Thetransistor 2100 is placed over the insulator 490. The insulator 492 isplaced over the transistor 2100. The insulator 494 is placed over theinsulator 492.

The insulator 464 includes an opening reaching the region 472 a, anopening reaching the region 472 b, and an opening reaching the conductor454. In the openings, the conductor 480 a, the conductor 480 b, and theconductor 480 c are embedded.

The insulator 466 includes an opening reaching the conductor 480 a, anopening reaching the conductor 480 b, and an opening reaching theconductor 480 c. In the openings, the conductor 478 a, the conductor 478b, and the conductor 478 c are embedded.

The insulator 468 includes an opening reaching the conductor 478 b andan opening reaching the conductor 478 c. In the openings, the conductor476 a and the conductor 476 b are embedded.

The insulator 490 includes an opening overlapping a channel formationregion of the transistor 2100, an opening reaching the conductor 476 a,and an opening reaching the conductor 476 b. In the openings, theconductor 474 a, the conductor 474 b, and the conductor 474 c areembedded.

The conductor 474 a may have a function of a gate electrode of thetransistor 2100. The electrical characteristics of the transistor 2100,such as the threshold voltage, may be controlled by application of apredetermined potential to the conductor 474 a, for example. Theconductor 474 a may be electrically connected to the conductor 404having a function of the gate electrode of the transistor 2100, forexample. In that case, on-state current of the transistor 2100 can beincreased. Furthermore, a punch-through phenomenon can be suppressed;thus, the electrical characteristics of the transistor 2100 in asaturation region can be stable.

The insulator 492 includes an opening reaching the conductor 474 bthrough the conductor 516 b that is one of a source electrode and adrain electrode of the transistor 2100, an opening reaching theconductor 516 a that is the other of the source electrode and the drainelectrode of the transistor 2100, an opening reaching the conductor 504that is the gate electrode of the transistor 2100, and an openingreaching the conductor 474 c. In the openings, the conductor 496 a, theconductor 496 b, the conductor 496 c, and the conductor 496 d areembedded. Note that in some cases, the openings are provided through anyof components of the transistor 2100 or the like.

The insulator 494 includes an opening reaching the conductor 496 a, anopening reaching the conductor 496 b and the conductor 496 d, and anopening reaching the conductor 496 c. In the openings, the conductor 498a, the conductor 498 b, and the conductor 498 c are embedded.

The insulators 464, 466, 468, 490, 492, and 494 may each be formed tohave, for example, a single-layer structure or a stacked-layer structureincluding an insulator containing boron, carbon, nitrogen, oxygen,fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon,gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium,or tantalum. The insulator 401 may be formed using, for example,aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride,silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide,yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide,hafnium oxide, or tantalum oxide.

The insulator that has a function of blocking oxygen and impurities suchas hydrogen is preferably included in at least one of the insulators464, 466, 468, 490, 492, and 494. When an insulator that has a functionof blocking oxygen and impurities such as hydrogen is placed near thetransistor 2100, the electrical characteristics of the transistor 2100can be stable.

An insulator with a function of blocking oxygen and impurities such ashydrogen may be formed to have a single-layer structure or astacked-layer structure including an insulator containing, for example,boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon,phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium,lanthanum, neodymium, hafnium, or tantalum.

Each of the conductor 480 a, the conductor 480 b, the conductor 480 c,the conductor 478 a, the conductor 478 b, the conductor 478 c, theconductor 476 a, the conductor 476 b, the conductor 474 a, the conductor474 b, the conductor 474 c, the conductor 496 a, the conductor 496 b,the conductor 496 c, the conductor 496 d, the conductor 498 a, theconductor 498 b, and the conductor 498 c may be formed to have, forexample, a single-layer structure or a stacked-layer structure includinga conductor containing one or more kinds selected from boron, nitrogen,oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium,manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium,molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. Analloy or a compound containing the above element may be used, forexample, and a conductor containing aluminum, a conductor containingcopper and titanium, a conductor containing copper and manganese, aconductor containing indium, tin, and oxygen, a conductor containingtitanium and nitrogen, or the like may be used.

Note that a semiconductor device in FIG. 26 is the same as thesemiconductor device in FIG. 25 except the structure of the transistor2200. Therefore, the description of the semiconductor device in FIG. 25is referred to for the semiconductor device in FIG. 26. In thesemiconductor device in FIG. 26, the transistor 2200 is a FIN-typetransistor. The effective channel width is increased in the FIN-typetransistor 2200, whereby the on-state characteristics of the transistor2200 can be improved. In addition, since contribution of the electricfield of the gate electrode can be increased, the off-statecharacteristics of the transistor 2200 can be improved.

Note that a semiconductor device in FIG. 27 is the same as thesemiconductor device in FIG. 25 except the structure of the transistor2200. Therefore, the description of the semiconductor device in FIG. 25is referred to for the semiconductor device in FIG. 27. Specifically, inthe semiconductor device in FIG. 27, the transistor 2200 is formed usingthe semiconductor substrate 450 which is an SOI substrate. In thestructure in FIG. 27, a region 456 is apart from the semiconductorsubstrate 450 with an insulator 452 provided therebetween. Since the SOIsubstrate is used as the semiconductor substrate 450, a punch-throughphenomenon and the like can be suppressed; thus, the off-statecharacteristics of the transistor 2200 can be improved. Note that theinsulator 452 can be formed by turning part of the semiconductorsubstrate 450 into an insulator. For example, silicon oxide can be usedas the insulator 452.

In each of the semiconductor devices shown in FIG. 25, FIG. 26, and FIG.27, a p-channel transistor is formed utilizing a semiconductorsubstrate, and an n-channel transistor is formed above that; therefore,an occupation area of the element can be reduced. That is, theintegration degree of the semiconductor device can be improved. Inaddition, the manufacturing process can be simplified compared to thecase where an n-channel transistor and a p-channel transistor are formedutilizing the same semiconductor substrate; therefore, the productivityof the semiconductor device can be increased. Moreover, the yield of thesemiconductor device can be improved. For the p-channel transistor, somecomplicated steps such as formation of lightly doped drain (LDD)regions, formation of a shallow trench structure, or distortion designcan be omitted in some cases. Therefore, the productivity and yield ofthe semiconductor device can be increased in some cases, compared to asemiconductor device where an n-channel transistor is formed utilizingthe semiconductor substrate.

<Memory Device 1>

An example of a semiconductor device (memory device) which includes thetransistor of one embodiment of the present invention, which can retainstored data even when not powered, and which has an unlimited number ofwrite cycles is shown in FIGS. 28A and 28B.

The semiconductor device illustrated in FIG. 28A includes a transistor3200 using a first semiconductor, a transistor 3300 using a secondsemiconductor, and a capacitor 3400. Note that any of theabove-described transistors can be used as the transistor 3300.

Note that the transistor 3300 is preferably a transistor with a lowoff-state current. For example, a transistor using an oxidesemiconductor can be used as the transistor 3300. Since the off-statecurrent of the transistor 3300 is low, stored data can be retained for along period at a predetermined node of the semiconductor device. Inother words, power consumption of the semiconductor device can bereduced because refresh operation becomes unnecessary or the frequencyof refresh operation can be extremely low.

In FIG. 28A, a first wiring 3001 is electrically connected to a sourceof the transistor 3200. A second wiring 3002 is electrically connectedto a drain of the transistor 3200. A third wiring 3003 is electricallyconnected to one of the source and the drain of the transistor 3300. Afourth wiring 3004 is electrically connected to the gate of thetransistor 3300. The gate of the transistor 3200 and the other of thesource and the drain of the transistor 3300 are electrically connectedto the one electrode of the capacitor 3400. A fifth wiring 3005 iselectrically connected to the other electrode of the capacitor 3400.

The semiconductor device in FIG. 28A has a feature that the potential ofthe gate of the transistor 3200 can be retained, and thus enableswriting, retaining, and reading of data as follows.

Writing and retaining of data are described. First, the potential of thefourth wiring 3004 is set to a potential at which the transistor 3300 ison, so that the transistor 3300 is turned on. Accordingly, the potentialof the third wiring 3003 is supplied to a node FG where the gate of thetransistor 3200 and the one electrode of the capacitor 3400 areelectrically connected to each other. That is, a predetermined charge issupplied to the gate of the transistor 3200 (writing). Here, one of twokinds of charges providing different potential levels (hereinafterreferred to as a low-level charge and a high-level charge) is supplied.After that, the potential of the fourth wiring 3004 is set to apotential at which the transistor 3300 is off, so that the transistor3300 is turned off. Thus, the charge is held at the node FG (retaining)

Since the off-state current of the transistor 3300 is low, the charge ofthe node FG is retained for a long time.

Next, reading of data is described. An appropriate potential (a readingpotential) is supplied to the fifth wiring 3005 while a predeterminedpotential (a constant potential) is supplied to the first wiring 3001,whereby the potential of the second wiring 3002 varies depending on theamount of charge retained in the node FG. This is because in the case ofusing an n-channel transistor as the transistor 3200, an apparentthreshold voltage V_(th) _(_) _(H) at the time when the high-levelcharge is given to the gate of the transistor 3200 is lower than anapparent threshold voltage V_(th) _(_) _(L) at the time when thelow-level charge is given to the gate of the transistor 3200. Here, anapparent threshold voltage refers to the potential of the fifth wiring3005 which is needed to make the transistor 3200 be in “on state”. Thus,the potential of the fifth wiring 3005 is set to a potential V₀ which isbetween V_(th) _(_) _(H) and V_(th) _(_) _(L), whereby charge suppliedto the node FG can be determined For example, in the case where thehigh-level charge is supplied to the node FG in writing and thepotential of the fifth wiring 3005 is V₀(>V_(th) _(_) _(H)), thetransistor 3200 is brought into “on state”. In the case where thelow-level charge is supplied to the node FG in writing, even when thepotential of the fifth wiring 3005 is V₀ (<V_(th) _(_) _(L)), thetransistor 3200 still remains in “off state”. Thus, the data retained inthe node FG can be read by determining the potential of the secondwiring 3002.

Note that in the case where memory cells are arrayed, it is necessarythat data of a desired memory cell be read in read operation. In thecase where data of the other memory cells is not read, the fifth wiring3005 may be supplied with a potential at which the transistor 3200 is in“off state” regardless of the charge supplied to the node FG, that is, apotential lower than V_(th) _(_) _(H). Alternatively, the fifth wiring3005 may be supplied with a potential at which the transistor 3200 isbrought into “on state” regardless of the charge supplied to the nodeFG, that is, a potential higher than V_(th) _(_) _(L).

<Memory Device 2>

The semiconductor device in FIG. 28B is different from the semiconductordevice in FIG. 28A in that the transistor 3200 is not provided. Also inthis case, data can be written and retained in a manner similar to thatof the semiconductor device in FIG. 28A.

Reading of data in the semiconductor device in FIG. 28B is described.When the transistor 3300 is brought into on state, the third wiring 3003which is in a floating state and the capacitor 3400 are brought intoconduction, and the charge is redistributed between the third wiring3003 and the capacitor 3400. As a result, the potential of the thirdwiring 3003 is changed. The amount of change in the potential of thethird wiring 3003 varies depending on the potential of the one electrodeof the capacitor 3400 (or the charge accumulated in the capacitor 3400).

For example, the potential of the third wiring 3003 after the chargeredistribution is (C_(B)×V_(B0)+C×V)/(C_(B)+C), where V is the potentialof the one electrode of the capacitor 3400, C is the capacitance of thecapacitor 3400, C_(B) is the capacitance component of the third wiring3003, and V_(B0) is the potential of the third wiring 3003 before thecharge redistribution. Thus, it can be found that, assuming that thememory cell is in either of two states in which the potential of the oneelectrode of the capacitor 3400 is V₁ and V₀(V₁>V₀), the potential ofthe third wiring 3003 in the case of retaining the potentialV₁(=(C_(B)×V_(B0)+C×V₁)/(C_(B)+C)) is higher than the potential of thethird wiring 3003 in the case of retaining the potentialV₀(=(C_(B)×V_(B0)+C×V₀)/(C_(B)+C)).

Then, by comparing the potential of the third wiring 3003 with apredetermined potential, data can be read.

In this case, a transistor including the first semiconductor may be usedfor a driver circuit for driving a memory cell, and a transistorincluding the second semiconductor may be stacked over the drivercircuit as the transistor 3300.

When including a transistor using an oxide semiconductor and having alow off-state current, the semiconductor device described above canretain stored data for a long time. In other words, power consumption ofthe semiconductor device can be reduced because refresh operationbecomes unnecessary or the frequency of refresh operation can beextremely low. Moreover, stored data can be retained for a long timeeven when power is not supplied (note that a potential is preferablyfixed).

In the semiconductor device, high voltage is not needed for writing dataand deterioration of elements is less likely to occur. Unlike in aconventional nonvolatile memory, for example, it is not necessary toinject and extract electrons into and from a floating gate; thus, aproblem such as deterioration of an insulator is not caused. That is,the semiconductor device of one embodiment of the present invention doesnot have a limit on the number of times data can be rewritten, which isa problem of a conventional nonvolatile memory, and the reliabilitythereof is drastically improved. Furthermore, data is written dependingon the on/off state of the transistor, whereby high-speed operation canbe achieved.

<Structure 2 of Semiconductor Device>

FIG. 29 is a cross-sectional view of the semiconductor device of FIG.28A. The semiconductor device shown in FIG. 29 includes the transistor3200, the transistor 3300, and the capacitor 3400. The transistor 3300and the capacitor 3400 are placed above the transistor 3200. Note thatfor the transistor 3300, the description of the above transistor 2100 isreferred to. Furthermore, for the transistor 3200, the description ofthe transistor 2200 in FIG. 25 is referred to. Note that although thetransistor 2200 is illustrated as a p-channel transistor in FIG. 25, thetransistor 3200 may be an n-channel transistor.

The transistor 3200 illustrated in FIG. 29 is a transistor using asemiconductor substrate 450. The transistor 3200 includes a region 472 ain the semiconductor substrate 450, a region 472 b in the semiconductorsubstrate 450, an insulator 462, and a conductor 454.

The semiconductor device illustrated in FIG. 29 includes insulators 464,466, and 468, conductors 480 a, 480 b, 480 c, 478 a, 478 b, 478 c, 476a, 476 b, 474 a, 474 b, 474 c, 496 a, 496 b, 496 c, 496 d, 498 a, 498 b,498 c, and 498 d, and insulators 490, 492, and 494.

The insulator 464 is provided over the transistor 3200. The insulator466 is provided over the insulator 464. The insulator 468 is providedover the insulator 466. The insulator 490 is provided over the insulator468. The transistor 3300 is provided over the insulator 490. Theinsulator 492 is provided over the transistor 3300. The insulator 494 isprovided over the insulator 492.

The insulator 464 has an opening reaching the region 472 a, an openingreaching the region 472 b, and an opening reaching the conductor 454. Inthe openings, the conductor 480 a, the conductor 480 b, and theconductor 480 c are embedded.

The insulator 466 includes an opening reaching the conductor 480 a, anopening reaching the conductor 480 b, and an opening reaching theconductor 480 c. In the openings, the conductor 478 a, the conductor 478b, and the conductor 478 c are embedded.

The insulator 468 includes an opening reaching the conductor 478 b andan opening reaching the conductor 478 c. In the openings, the conductor476 a and the conductor 476 b are embedded.

The insulator 490 includes an opening overlapping the channel formationregion of the transistor 3300, an opening reaching the conductor 476 a,and an opening reaching the conductor 476 b. In the openings, theconductors 474 a, the conductor 474 b, and the conductor 474 c areembedded.

The conductor 474 a may have a function as a bottom gate electrode ofthe transistor 3300. Alternatively, for example, electriccharacteristics such as the threshold voltage of the transistor 3300 maybe controlled by application of a predetermined potential to theconductor 474 a. Further alternatively, for example, the conductor 474 aand the conductor 404 that is the top gate electrode of the transistor3300 may be electrically connected to each other. Thus, the on-statecurrent of the transistor 3300 can be increased. A punch-throughphenomenon can be suppressed; thus, stable electric characteristics inthe saturation region of the transistor 3300 can be obtained.

The insulator 492 includes an opening reaching the conductor 474 bthrough the conductor 516 b that is one of a source electrode and adrain electrode of the transistor 3300, an opening reaching theconductor 514 that overlaps the conductor 516 a that is the other of thesource electrode and the drain electrode of the transistor 3300, withthe insulator 511 positioned therebetween, an opening reaching theconductor 504 that is the gate electrode of the transistor 3300, and anopening reaching the conductor 474 c through the conductor 516 a that isthe other of the source electrode and the drain electrode of thetransistor 3300. In the openings, the conductor 496 a, the conductor 496b, the conductor 496 c, and the conductor 496 d are embedded. Note thatin some cases, a component of the transistor 3300 or the like is throughother components.

The insulator 494 includes an opening reaching the conductor 496 a, anopening reaching the conductors 496 b, an opening reaching the conductor496 c, and an opening reaching the conductor 496 d. In the openings, theconductors 498 a, 498 b, 498 c, and 498 d are embedded.

At least one of the insulators 464, 466, 468, 490, 492, and 494preferably has a function of blocking oxygen and impurities such ashydrogen. When an insulator that has a function of blocking oxygen andimpurities such as hydrogen is placed near the transistor 3300, theelectrical characteristics of the transistor 3300 can be stable.

The conductor 498 d may be formed to have a single-layer structure or astacked-layer structure including a conductor containing, for example,one or more kinds selected from boron, nitrogen, oxygen, fluorine,silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt,nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum,ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or acompound of the above element may be used, for example, and a conductorcontaining aluminum, a conductor containing copper and titanium, aconductor containing copper and manganese, a conductor containingindium, tin, and oxygen, a conductor containing titanium and nitrogen,or the like may be used.

The source or drain of the transistor 3200 is electrically connected tothe conductor 516 b that is one of a source electrode and a drainelectrode of the transistor 3300 through the conductor 480 b, theconductor 478 b, the conductor 476 a, the conductor 474 b, and theconductor 496 c. The conductor 454 that is the gate electrode of thetransistor 3200 is electrically connected to the conductor 516 a that isthe other of the source electrode and the drain electrode of thetransistor 3300 through the conductor 480 c, the conductor 478 c, theconductor 476 b, the conductor 474 c, and the conductor 496 d.

The capacitor 3400 includes an electrode electrically connected to theother of the source electrode and the drain electrode of the transistor3300, the conductor 514, and an insulator 511. Because the insulator 511can be formed in the same step as the insulator 512 that functions as agate insulator of the transistor 3300, productivity can be preferablyincreased in some cases. When a layer formed in the same step as theconductor 504 that functions as a gate electrode of the transistor 3300is used as the conductor 514, productivity can be preferably increasedin some cases.

For the structures of other components, the description of FIG. 25 andthe like can be referred to as appropriate.

A semiconductor device in FIG. 30 is the same as the semiconductordevice in FIG. 29 except the structure of the transistor 3200.Therefore, the description of the semiconductor device in FIG. 29 isreferred to for the semiconductor device in FIG. 30. Specifically, inthe semiconductor device in FIG. 30, the transistor 3200 is a FIN-typetransistor. For the FIN-type transistor 3200, the description of thetransistor 2200 in FIG. 26 is referred to. Note that although thetransistor 2200 is illustrated as a p-channel transistor in FIG. 26, thetransistor 3200 may be an n-channel transistor.

A semiconductor device in FIG. 31 is the same as the semiconductordevice in FIG. 29 except a structure of the transistor 3200. Therefore,the description of the semiconductor device in FIG. 29 is referred tofor the semiconductor device in FIG. 31. Specifically, in thesemiconductor device in FIG. 31, the transistor 3200 is provided in thesemiconductor substrate 450 that is an SOI substrate. For the transistor3200, which is provided in the semiconductor substrate 450 that is anSOI substrate, the description of the transistor 2200 in FIG. 27 isreferred to. Note that although the transistor 2200 is illustrated as ap-channel transistor in FIG. 27, the transistor 3200 may be an n-channeltransistor.

<Imaging Device>

An imaging device of one embodiment of the present invention isdescribed below.

FIG. 32A is a plan view illustrating an example of an imaging device 200of one embodiment of the present invention. The imaging device 200includes a pixel portion 210 and peripheral circuits for driving thepixel portion 210 (a peripheral circuit 260, a peripheral circuit 270, aperipheral circuit 280, and a peripheral circuit 290). The pixel portion210 includes a plurality of pixels 211 arranged in a matrix with p rowsand q columns (p and q are each a natural number greater than or equalto 2). The peripheral circuit 260, the peripheral circuit 270, theperipheral circuit 280, and the peripheral circuit 290 are eachconnected to a plurality of pixels 211, and a signal for driving theplurality of pixels 211 is supplied. In this specification and the like,in some cases, “a peripheral circuit” or “a driver circuit” indicatesall of the peripheral circuits 260, 270, 280, and 290. For example, theperipheral circuit 260 can be regarded as part of the peripheralcircuit.

The imaging device 200 preferably includes a light source 291. The lightsource 291 can emit detection light P1.

The peripheral circuit includes at least one of a logic circuit, aswitch, a buffer, an amplifier circuit, and a converter circuit. Theperipheral circuit may be provided over a substrate where the pixelportion 210 is formed. Part or the whole of the peripheral circuit maybe mounted using a semiconductor device such as an IC. Note that as theperipheral circuit, one or more of the peripheral circuits 260, 270,280, and 290 may be omitted.

As illustrated in FIG. 32B, the pixels 211 may be provided to beinclined in the pixel portion 210 included in the imaging device 200.When the pixels 211 are obliquely arranged, the distance between pixels(pitch) can be shortened in the row direction and the column direction.Accordingly, the quality of an image taken with the imaging device 200can be improved.

CONFIGURATION EXAMPLE 1 OF PIXEL

The pixel 211 included in the imaging device 200 is formed with aplurality of subpixels 212, and each subpixel 212 is combined with afilter which transmits light with a specific wavelength band (colorfilter), whereby data for achieving color image display can be obtained.

FIG. 33A is a plan view showing an example of the pixel 211 with which acolor image is obtained. The pixel 211 illustrated in FIG. 33A includesa subpixel 212 provided with a color filter transmitting light with ared (R) wavelength band (also referred to as a subpixel 212R), asubpixel 212 provided with a color filter transmitting light with agreen (G) wavelength band (also referred to as a subpixel 212G), and asubpixel 212 provided with a color filter transmitting light with a blue(B) wavelength band (also referred to as a subpixel 212B). The subpixel212 can function as a photosensor.

The subpixel 212 (the subpixel 212R, the subpixel 212G, and the subpixel212B) is electrically connected to a wiring 231, a wiring 247, a wiring248, a wiring 249, and a wiring 250. In addition, the subpixel 212R, thesubpixel 212G, and the subpixel 212B are connected to respective wirings253 which are independent from one another. In this specification andthe like, for example, the wiring 248 and the wiring 249 that areconnected to the pixel 211 in the n-th row (n is an integer greater thanor equal to 1 and less than or equal to p) are referred to as a wiring248[n] and a wiring 249[n]. For example, the wiring 253 connected to thepixel 211 in the m-th column (m is an integer greater than or equal to 1and less than or equal to q) is referred to as a wiring 253[m]. Notethat in FIG. 33A, the wirings 253 connected to the subpixel 212R, thesubpixel 212G, and the subpixel 212B in the pixel 211 in the m-th columnare referred to as a wiring 253[m]R, a wiring 253[m]G, and a wiring253[m]B. The subpixels 212 are electrically connected to the peripheralcircuit through the above wirings.

The imaging device 200 has a structure in which the subpixel 212 iselectrically connected to the subpixel 212 in an adjacent pixel 211which is provided with a color filter transmitting light with the samewavelength band as the subpixel 212, via a switch. FIG. 33B shows aconnection example of the subpixels 212: the subpixel 212 in the pixel211 arranged in an n-th row and an m-th column and the subpixel 212 inthe adjacent pixel 211 arranged in an (n+1)-th row and the m-th column.In FIG. 33B, the subpixel 212R arranged in the n-th row and the m-thcolumn and the subpixel 212R arranged in the (n+1)-th row and the m-thcolumn are connected to each other via a switch 201. The subpixel 212Garranged in the n-th row and the m-th column and the subpixel 212Garranged in the (n+1)-th row and the m-th column are connected to eachother via a switch 202. The subpixel 212B arranged in the n-th row andthe m-th column and the subpixel 212B arranged in the (n+1)-th row andthe m-th column are connected to each other via a switch 203.

The color filter used in the subpixel 212 is not limited to red (R),green (G), and blue (B) color filters, and color filters that transmitlight of cyan (C), yellow (Y), and magenta (M) may be used. By provisionof the subpixels 212 that sense light with three different wavelengthbands in one pixel 211, a full-color image can be obtained.

The pixel 211 including the subpixel 212 provided with a color filtertransmitting yellow (Y) light may be provided, in addition to thesubpixels 212 provided with the color filters transmitting red (R),green (G), and blue (B) light. The pixel 211 including the subpixel 212provided with a color filter transmitting blue (B) light may beprovided, in addition to the subpixels 212 provided with the colorfilters transmitting cyan (C), yellow (Y), and magenta (M) light. Whenthe subpixels 212 sensing light with four different wavelength bands areprovided in one pixel 211, the reproducibility of colors of an obtainedimage can be increased.

For example, in FIG. 33A, in regard to the subpixel 212 sensing a redwavelength band, the subpixel 212 sensing a green wavelength band, andthe subpixel 212 sensing a blue wavelength band, the pixel number ratio(or the light receiving area ratio) thereof is not necessarily 1:1:1.For example, the Bayer arrangement in which the pixel number ratio (thelight receiving area ratio) is set at red:green:blue=1:2:1 may beemployed. Alternatively, the pixel number ratio (the light receivingarea ratio) of red and green to blue may be 1:6:1.

Although the number of subpixels 212 provided in the pixel 211 may beone, two or more subpixels are preferably provided. For example, whentwo or more subpixels 212 sensing the same wavelength band are provided,the redundancy is increased, and the reliability of the imaging device200 can be increased.

When an infrared (IR) filter that transmits infrared light and absorbsor reflects visible light is used as the filter, the imaging device 200that senses infrared light can be achieved.

Furthermore, when a neutral density (ND) filter (dark filter) is used,output saturation which occurs when a large amount of light enters aphotoelectric conversion element (light-receiving element) can beprevented. With a combination of ND filters with different dimmingcapabilities, the dynamic range of the imaging device can be increased.

Besides the above-described filter, the pixel 211 may be provided with alens. An arrangement example of the pixel 211, a filter 254, and a lens255 is described with cross-sectional views in FIGS. 34A and 34B. Withthe lens 255, the photoelectric conversion element can receive incidentlight efficiently. Specifically, as illustrated in FIG. 34A, light 256enters a photoelectric conversion element 220 through the lens 255, thefilter 254 (a filter 254R, a filter 254G, and a filter 254B), a pixelcircuit 230, and the like which are provided in the pixel 211.

However, as indicated by a region surrounded with dashed-dotted lines,part of the light 256 indicated by arrows might be blocked by somewirings 257. Thus, a preferable structure is that the lens 255 and thefilter 254 are provided on the photoelectric conversion element 220side, so that the photoelectric conversion element 220 can efficientlyreceive the light 256 as illustrated in FIG. 34B. When the light 256enters the photoelectric conversion element 220 from the photoelectricconversion element 220 side, the imaging device 200 with highsensitivity can be provided.

As the photoelectric conversion element 220 illustrated in FIGS. 34A and34B, a photoelectric conversion element in which a p-n junction or ap-i-n junction is formed may be used.

The photoelectric conversion element 220 may be formed using a substancethat has a function of absorbing a radiation and generating electriccharges. Examples of the substance that has a function of absorbing aradiation and generating electric charges include selenium, lead iodide,mercury iodide, gallium arsenide, cadmium telluride, and cadmium zincalloy.

For example, when selenium is used for the photoelectric conversionelement 220, the photoelectric conversion element 220 can have a lightabsorption coefficient in a wide wavelength range, such as visiblelight, ultraviolet light, infrared light, X-rays, and gamma rays.

One pixel 211 included in the imaging device 200 may include thesubpixel 212 with a first filter in addition to the subpixel 212illustrated in FIGS. 33A and 33B.

CONFIGURATION EXAMPLE 2 OF PIXEL

An example of a pixel including a transistor using silicon and atransistor using an oxide semiconductor is described below.

FIGS. 35A and 35B are each a cross-sectional view of an element includedin an imaging device. The imaging device illustrated in FIG. 35Aincludes a transistor 351 including silicon over a silicon substrate300, transistors 352 and 353 which include an oxide semiconductor andare stacked over the transistor 351, and a photodiode 360 provided in asilicon substrate 300. The transistors and the photodiode 360 areelectrically connected to various plugs 370 and wirings 371. Inaddition, an anode 361 of the photodiode 360 is electrically connectedto the plug 370 through a low-resistance region 363.

The imaging device includes a layer 310 including the transistor 351provided on the silicon substrate 300 and the photodiode 360 provided inthe silicon substrate 300, a layer 320 which is in contact with thelayer 310 and includes the wirings 371, a layer 330 which is in contactwith the layer 320 and includes the transistors 352 and 353, and a layer340 which is in contact with the layer 330 and includes a wiring 372 anda wiring 373.

In the example of cross-sectional view in FIG. 35A, a light-receivingsurface of the photodiode 360 is provided on the side opposite to asurface of the silicon substrate 300 where the transistor 351 is formed.With this structure, a light path can be secured without an influence ofthe transistors and the wirings. Thus, a pixel with a high apertureratio can be formed. Note that the light-receiving surface of thephotodiode 360 can be the same as the surface where the transistor 351is formed.

In the case where a pixel is formed with use of only transistors usingan oxide semiconductor, the layer 310 may include the transistor usingan oxide semiconductor. Alternatively, the layer 310 may be omitted, andthe pixel may be formed with use of only transistors using an oxidesemiconductor.

In the case where a pixel is formed with use of only transistors usingsilicon, the layer 330 may be omitted. An example of a cross-sectionalview in which the layer 330 is not provided is shown in FIG. 35B.

Note that the silicon substrate 300 may be an SOI substrate.Furthermore, the silicon substrate 300 can be replaced with a substratemade of germanium, silicon germanium, silicon carbide, gallium arsenide,aluminum gallium arsenide, indium phosphide, gallium nitride, or anorganic semiconductor.

Here, an insulator 380 is provided between the layer 310 including thetransistor 351 and the photodiode 360 and the layer 330 including thetransistors 352 and 353. However, there is no limitation on the positionof the insulator 380.

Hydrogen in an insulator provided in the vicinity of a channel formationregion of the transistor 351 terminates dangling bonds of silicon;accordingly, the reliability of the transistor 351 can be improved. Incontrast, hydrogen in the insulator provided in the vicinity of thetransistor 352, the transistor 353, and the like becomes one of factorsgenerating a carrier in the oxide semiconductor. Thus, the hydrogen maycause a reduction of the reliability of the transistor 352, thetransistor 353, and the like. Therefore, in the case where thetransistor using an oxide semiconductor is provided over the transistorusing a silicon-based semiconductor, it is preferable that the insulator380 having a function of blocking hydrogen be provided between thetransistors. When the hydrogen is confined below the insulator 380, thereliability of the transistor 351 can be improved. In addition, thehydrogen can be prevented from being diffused from a part below theinsulator 380 to a part above the insulator 380; thus, the reliabilityof the transistor 352, the transistor 353, and the like can beincreased.

As the insulator 380, an insulator having a function of blocking oxygenor hydrogen is used, for example.

In the cross-sectional view in FIG. 35A, the photodiode 360 in the layer310 and the transistor in the layer 330 can be formed so as to overlapeach other. Thus, the degree of integration of pixels can be increased.In other words, the resolution of the imaging device can be increased.

As illustrated in FIG. 36A1 and FIG. 36B1, part or the whole of theimaging device can be bent. FIG. 36A1 illustrates a state in which theimaging device is bent in the direction of a dashed-dotted line X1-X2.FIG. 36A2 is a cross-sectional view illustrating a portion indicated bythe dashed-dotted line X1-X2 in FIG. 36A1. FIG. 36A3 is across-sectional view illustrating a portion indicated by a dashed-dottedline Y1-Y2 in FIG. 36A1.

FIG. 36B1 illustrates a state where the imaging device is bent in thedirection of a dashed-dotted chain X3-X4 and the direction of adashed-dotted line Y3-Y4. FIG. 36B2 is a cross-sectional viewillustrating a portion indicated by the dashed-dotted line X3-X4 in FIG.36B1. FIG. 36B3 is a cross-sectional view illustrating a portionindicated by the dashed-dotted line Y3-Y4 in FIG. 36B1.

The bent imaging device enables the curvature of field and astigmatismto be reduced. Thus, the optical design of lens and the like, which isused in combination of the imaging device, can be facilitated. Forexample, the number of lens used for aberration correction can bereduced; accordingly, a reduction of size or weight of electronicdevices using the imaging device, and the like, can be achieved. Inaddition, the quality of a captured image can be improved.

<CPU>

A CPU including a semiconductor device such as any of theabove-described transistors or the above-described memory device isdescribed below.

FIG. 37 is a block diagram illustrating a configuration example of a CPUincluding any of the above-described transistors as a component.

The CPU illustrated in FIG. 37 includes, over a substrate 1190, anarithmetic logic unit (ALU) 1191, an ALU controller 1192, an instructiondecoder 1193, an interrupt controller 1194, a timing controller 1195, aregister 1196, a register controller 1197, a bus interface 1198, arewritable ROM 1199, and a ROM interface 1189. A semiconductorsubstrate, an SOI substrate, a glass substrate, or the like is used asthe substrate 1190. The ROM 1199 and the ROM interface 1189 may beprovided over a separate chip. Needless to say, the CPU in FIG. 37 isjust an example in which the configuration has been simplified, and anactual CPU may have a variety of configurations depending on theapplication. For example, the CPU may have the following configuration:a structure including the CPU illustrated in FIG. 37 or an arithmeticcircuit is considered as one core; a plurality of such cores areincluded; and the cores operate in parallel. The number of bits that theCPU can process in an internal arithmetic circuit or in a data bus canbe 8, 16, 32, or 64, for example.

An instruction that is input to the CPU through the bus interface 1198is input to the instruction decoder 1193 and decoded therein, and then,input to the ALU controller 1192, the interrupt controller 1194, theregister controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the registercontroller 1197, and the timing controller 1195 conduct various controlsin accordance with the decoded instruction. Specifically, the ALUcontroller 1192 generates signals for controlling the operation of theALU 1191. While the CPU is executing a program, the interrupt controller1194 judges an interrupt request from an external input/output device ora peripheral circuit on the basis of its priority or a mask state, andprocesses the request. The register controller 1197 generates an addressof the register 1196, and reads/writes data from/to the register 1196 inaccordance with the state of the CPU.

The timing controller 1195 generates signals for controlling operationtimings of the ALU 1191, the ALU controller 1192, the instructiondecoder 1193, the interrupt controller 1194, and the register controller1197. For example, the timing controller 1195 includes an internal clockgenerator for generating an internal clock signal based on a referenceclock signal, and supplies the internal clock signal to the abovecircuits.

In the CPU illustrated in FIG. 37, a memory cell is provided in theregister 1196. For the memory cell of the register 1196, any of theabove-described transistors, the above-described memory device, or thelike can be used.

In the CPU illustrated in FIG. 37, the register controller 1197 selectsoperation of retaining data in the register 1196 in accordance with aninstruction from the ALU 1191. That is, the register controller 1197selects whether data is retained by a flip-flop or by a capacitor in thememory cell included in the register 1196. When data retention by theflip-flop is selected, a power supply voltage is supplied to the memorycell in the register 1196. When data retention by the capacitor isselected, the data is rewritten in the capacitor, and supply of a powersupply voltage to the memory cell in the register 1196 can be stopped.

FIG. 38 is an example of a circuit diagram of a memory element 1200 thatcan be used as the register 1196. The memory element 1200 includes acircuit 1201 in which stored data is volatile when power supply isstopped, a circuit 1202 in which stored data is nonvolatile even whenpower supply is stopped, a switch 1203, a switch 1204, a logic element1206, a capacitor 1207, and a circuit 1220 having a selecting function.The circuit 1202 includes a capacitor 1208, a transistor 1209, and atransistor 1210. Note that the memory element 1200 may further includeanother element such as a diode, a resistor, or an inductor, as needed.

Here, the above-described memory device can be used as the circuit 1202.When supply of a power supply voltage to the memory element 1200 isstopped, GND (0 V) or a potential at which the transistor 1209 in thecircuit 1202 is turned off continues to be input to a gate of thetransistor 1209. For example, the gate of the transistor 1209 isgrounded through a load such as a resistor.

Shown here is an example in which the switch 1203 is a transistor 1213having one conductivity type (e.g., an n-channel transistor) and theswitch 1204 is a transistor 1214 having a conductivity type opposite tothe one conductivity type (e.g., a p-channel transistor). A firstterminal of the switch 1203 corresponds to one of a source and a drainof the transistor 1213, a second terminal of the switch 1203 correspondsto the other of the source and the drain of the transistor 1213, andconduction or non-conduction between the first terminal and the secondterminal of the switch 1203 (i.e., the on/off state of the transistor1213) is selected by a control signal RD input to a gate of thetransistor 1213. A first terminal of the switch 1204 corresponds to oneof a source and a drain of the transistor 1214, a second terminal of theswitch 1204 corresponds to the other of the source and the drain of thetransistor 1214, and conduction or non-conduction between the firstterminal and the second terminal of the switch 1204 (i.e., the on/offstate of the transistor 1214) is selected by the control signal RD inputto a gate of the transistor 1214.

One of a source and a drain of the transistor 1209 is electricallyconnected to one of a pair of electrodes of the capacitor 1208 and agate of the transistor 1210. Here, the connection portion is referred toas a node M2. One of a source and a drain of the transistor 1210 iselectrically connected to a line which can supply a low power supplypotential (e.g., a GND line), and the other thereof is electricallyconnected to the first terminal of the switch 1203 (the one of thesource and the drain of the transistor 1213). The second terminal of theswitch 1203 (the other of the source and the drain of the transistor1213) is electrically connected to the first terminal of the switch 1204(the one of the source and the drain of the transistor 1214). The secondterminal of the switch 1204 (the other of the source and the drain ofthe transistor 1214) is electrically connected to a line which cansupply a power supply potential VDD. The second terminal of the switch1203 (the other of the source and the drain of the transistor 1213), thefirst terminal of the switch 1204 (the one of the source and the drainof the transistor 1214), an input terminal of the logic element 1206,and one of a pair of electrodes of the capacitor 1207 are electricallyconnected to each other. Here, the connection portion is referred to asa node M1. The other of the pair of electrodes of the capacitor 1207 canbe supplied with a constant potential. For example, the other of thepair of electrodes of the capacitor 1207 can be supplied with a lowpower supply potential (e.g., GND) or a high power supply potential(e.g., VDD). The other of the pair of electrodes of the capacitor 1207is electrically connected to the line which can supply a low powersupply potential (e.g., a GND line). The other of the pair of electrodesof the capacitor 1208 can be supplied with a constant potential. Forexample, the other of the pair of electrodes of the capacitor 1208 canbe supplied with the low power supply potential (e.g., GND) or the highpower supply potential (e.g., VDD). The other of the pair of electrodesof the capacitor 1208 is electrically connected to the line which cansupply a low power supply potential (e.g., a GND line).

The capacitor 1207 and the capacitor 1208 are not necessarily providedas long as the parasitic capacitance of the transistor, the wiring, orthe like is actively utilized.

A control signal WE is input to the gate of the transistor 1209. As foreach of the switch 1203 and the switch 1204, a conduction state or anon-conduction state between the first terminal and the second terminalis selected by the control signal RD which is different from the controlsignal WE. When the first terminal and the second terminal of one of theswitches are in the conduction state, the first terminal and the secondterminal of the other of the switches are in the non-conduction state.

A signal corresponding to data retained in the circuit 1201 is input tothe other of the source and the drain of the transistor 1209. FIG. 38illustrates an example in which a signal output from the circuit 1201 isinput to the other of the source and the drain of the transistor 1209.The logic value of a signal output from the second terminal of theswitch 1203 (the other of the source and the drain of the transistor1213) is inverted by the logic element 1206, and the inverted signal isinput to the circuit 1201 through the circuit 1220.

In the example of FIG. 38, a signal output from the second terminal ofthe switch 1203 (the other of the source and the drain of the transistor1213) is input to the circuit 1201 through the logic element 1206 andthe circuit 1220; however, one embodiment of the present invention isnot limited thereto. The signal output from the second terminal of theswitch 1203 (the other of the source and the drain of the transistor1213) may be input to the circuit 1201 without its logic value beinginverted. For example, in the case where the circuit 1201 includes anode in which a signal obtained by inversion of the logic value of asignal input from the input terminal is retained, the signal output fromthe second terminal of the switch 1203 (the other of the source and thedrain of the transistor 1213) can be input to the node.

In FIG. 38, the transistors included in the memory element 1200 exceptfor the transistor 1209 can each be a transistor in which a channel isformed in a layer formed using a semiconductor other than an oxidesemiconductor or in the substrate 1190. For example, the transistor canbe a transistor whose channel is formed in a silicon film or a siliconsubstrate. Alternatively, all the transistors in the memory element 1200may be a transistor in which a channel is formed in an oxidesemiconductor. Further alternatively, in the memory element 1200, atransistor in which a channel is formed in an oxide semiconductor may beincluded besides the transistor 1209, and a transistor in which achannel is formed in a layer formed using a semiconductor other than anoxide semiconductor or in the substrate 1190 can be used for the rest ofthe transistors.

As the circuit 1201 in FIG. 38, for example, a flip-flop circuit can beused. As the logic element 1206, for example, an inverter or a clockedinverter can be used.

In a period during which the memory element 1200 is not supplied withthe power supply voltage, the semiconductor device of one embodiment ofthe present invention can retain data stored in the circuit 1201 by thecapacitor 1208 which is provided in the circuit 1202.

The off-state current of a transistor in which a channel is formed in anoxide semiconductor is extremely low. For example, the off-state currentof a transistor in which a channel is formed in an oxide semiconductoris significantly lower than that of a transistor in which a channel isformed in silicon having crystallinity. Thus, when the transistor isused as the transistor 1209, a signal held in the capacitor 1208 isretained for a long time also in a period during which the power supplyvoltage is not supplied to the memory element 1200. The memory element1200 can accordingly retain the stored content (data) also in a periodduring which the supply of the power supply voltage is stopped.

Since the above-described memory element performs pre-charge operationwith the switch 1203 and the switch 1204, the time required for thecircuit 1201 to retain original data again after the supply of the powersupply voltage is restarted can be shortened.

In the circuit 1202, a signal retained by the capacitor 1208 is input tothe gate of the transistor 1210. Therefore, after supply of the powersupply voltage to the memory element 1200 is restarted, the signalretained by the capacitor 1208 can be converted into the onecorresponding to the state (the on state or the off state) of thetransistor 1210 to be read from the circuit 1202. Consequently, anoriginal signal can be accurately read even when a potentialcorresponding to the signal retained by the capacitor 1208 varies tosome degree.

By applying the above-described memory element 1200 to a memory devicesuch as a register or a cache memory included in a processor, data inthe memory device can be prevented from being lost owing to the stop ofthe supply of the power supply voltage. Furthermore, shortly after thesupply of the power supply voltage is restarted, the memory device canbe returned to the same state as that before the power supply isstopped. Therefore, the power supply can be stopped even for a shorttime in the processor or one or a plurality of logic circuits includedin the processor, resulting in lower power consumption.

Although the memory element 1200 is used in a CPU, the memory element1200 can also be used in an LSI such as a digital signal processor(DSP), a custom LSI, or a programmable logic device (PLD), and a radiofrequency (RF) device.

<Display Device>

A display device of one embodiment of the present invention is describedbelow with reference to FIGS. 39A to 39C and FIGS. 40A and 40B.

Examples of a display element provided in the display device include aliquid crystal element (also referred to as a liquid crystal displayelement) and a light-emitting element (also referred to as alight-emitting display element). The light-emitting element includes, inits category, an element whose luminance is controlled by a current orvoltage, and specifically includes, in its category, an inorganicelectroluminescent (EL) element, an organic EL element, and the like. Adisplay device including an EL element (EL display device) and a displaydevice including a liquid crystal element (liquid crystal displaydevice) are described below as examples of the display device.

Note that the display device described below includes in its category apanel in which a display element is sealed and a module in which an ICsuch as a controller is mounted on the panel.

The display device described below refers to an image display device ora light source (including a lighting device). The display deviceincludes any of the following modules: a module provided with aconnector such as an FPC or TCP; a module in which a printed board isprovided at the end of TCP; and a module in which an integrated circuit(IC) is mounted directly on a display element by a COG method.

FIGS. 39A to 39C illustrate an example of an EL display device of oneembodiment of the present invention. FIG. 39A is a circuit diagram of apixel in an EL display device. FIG. 39B is a plan view showing the wholeof the EL display device. FIG. 39C is a cross-sectional view taken alongpart of dashed-dotted line M-N in FIG. 39B.

FIG. 39A illustrates an example of a circuit diagram of a pixel used inan EL display device.

Note that in this specification and the like, it might be possible forthose skilled in the art to constitute one embodiment of the inventioneven when portions to which all the terminals of an active element(e.g., a transistor or a diode), a passive element (e.g., a capacitor ora resistor), or the like are connected are not specified. In otherwords, one embodiment of the invention can be clear even when connectionportions are not specified. Further, in the case where a connectionportion is disclosed in this specification and the like, it can bedetermined that one embodiment of the invention in which a connectionportion is not specified is disclosed in this specification and thelike, in some cases. Particularly in the case where the number ofportions to which a terminal is connected might be more than one, it isnot necessary to specify the portions to which the terminal isconnected. Therefore, it might be possible to constitute one embodimentof the invention by specifying only portions to which some of terminalsof an active element (e.g., a transistor or a diode), a passive element(e.g., a capacitor or a resistor), or the like are connected.

Note that in this specification and the like, it might be possible forthose skilled in the art to specify the invention when at least theconnection portion of a circuit is specified. Alternatively, it might bepossible for those skilled in the art to specify the invention when atleast a function of a circuit is specified. In other words, when afunction of a circuit is specified, one embodiment of the presentinvention can be clear. Further, it can be determined that oneembodiment of the present invention whose function is specified isdisclosed in this specification and the like. Therefore, when aconnection portion of a circuit is specified, the circuit is disclosedas one embodiment of the invention even when a function is notspecified, and one embodiment of the invention can be constituted.Alternatively, when a function of a circuit is specified, the circuit isdisclosed as one embodiment of the invention even when a connectionportion is not specified, and one embodiment of the invention can beconstituted.

The EL display device illustrated in FIG. 39A includes a switchingelement 743, a transistor 741, a capacitor 742, and a light-emittingelement 719.

Note that FIG. 39A and the like each illustrate an example of a circuitstructure; therefore, a transistor can be provided additionally. Incontrast, for each node in FIG.

39A and the like, it is possible not to provide an additionaltransistor, switch, passive element, or the like.

A gate of the transistor 741 is electrically connected to one terminalof the switching element 743 and one electrode of the capacitor 742. Asource of the transistor 741 is electrically connected to the otherelectrode of the capacitor 742 and one electrode of the light-emittingelement 719. A drain of the transistor 741 is supplied with a powersupply potential VDD. The other terminal of the switching element 743 iselectrically connected to a signal line 744. A constant potential issupplied to the other electrode of the light-emitting element 719. Theconstant potential is a ground potential GND or a potential lower thanthe ground potential GND.

It is preferable to use a transistor as the switching element 743. Whenthe transistor is used as the switching element, the area of a pixel canbe reduced, so that the EL display device can have high resolution. Asthe switching element 743, a transistor formed through the same step asthe transistor 741 can be used, so that EL display devices can bemanufactured with high productivity. Note that as the transistor 741and/or the switching element 743, any of the above-described transistorscan be used, for example.

FIG. 39B is a plan view of the EL display device. The EL display deviceincludes a substrate 700, a substrate 750, a sealant 734, a drivercircuit 735, a driver circuit 736, a pixel 737, and an FPC 732. Thesealant 734 is provided between the substrate 700 and the substrate 750so as to surround the pixel 737, the driver circuit 735, and the drivercircuit 736. Note that the driver circuit 735 and/or the driver circuit736 may be provided outside the sealant 734.

FIG. 39C is a cross-sectional view of the EL display device taken alongpart of dashed-dotted line M-N in FIG. 39B.

FIG. 39C illustrates a structure of the transistor 741 including aconductor 704 a over the substrate 700; an insulator 712 a over theconductor 704 a; an insulator 712 b over the insulator 712 a; asemiconductor 706 a and a semiconductor 706 b which are over theinsulator 712 b and overlaps the conductor 704 a; a conductor 716 a anda conductor 716 b in contact with the semiconductors 706 a and 706 b; aninsulator 718 a over the semiconductor 706 b, the conductor 716 a, andthe conductor 716 b; an insulator 718 b over the insulator 718 a; aninsulator 718 c over the insulator 718 b; and a conductor 714 a that isover the insulator 718 c and overlaps the semiconductor 706 b. Note thatthe structure of the transistor 741 is just an example; the transistor741 may have a structure different from that illustrated in FIG. 39C.

Thus, in the transistor 741 illustrated in FIG. 39C, the conductor 704 aserves as a gate electrode, the insulator 712 a and the insulator 712 bserve as a gate insulator, the conductor 716 a serves as a sourceelectrode, the conductor 716 b serves as a drain electrode, theinsulator 718 a, the insulator 718 b, and the insulator 718 c serve as agate insulator, and the conductor 714 a serves as a gate electrode. Notethat in some cases, electrical characteristics of the semiconductors 706a and 706 b change if light enters the semiconductor. To prevent this,it is preferable that one or more of the conductor 704 a, the conductor716 a, the conductor 716 b, and the conductor 714 a have alight-blocking property.

Note that the interface between the insulator 718 a and the insulator718 b is indicated by a broken line. This means that the boundarybetween them is not clear in some cases. For example, in the case wherethe insulator 718 a and the insulator 718 b are formed using insulatorsof the same kind, the insulator 718 a and the insulator 718 b are notdistinguished from each other in some cases depending on an observationmethod.

FIG. 39C illustrates a structure of the capacitor 742 including aconductor 704 b over the substrate; the insulator 712 a over theconductor 704 b; the insulator 712 b over the insulator 712 a; theconductor 716 a that is over the insulator 712 b and overlaps theconductor 704 b; the insulator 718 a over the conductor 716 a; theinsulator 718 b over the insulator 718 a; the insulator 718 c over theinsulator 718 b; and a conductor 714 b that is over the insulator 718 cand overlaps the conductor 716 a. In this structure, part of theinsulator 718 a and part of the insulator 718 b are removed in a regionwhere the conductor 716 a and the conductor 714 b overlap each other.

In the capacitor 742, each of the conductor 704 b and the conductor 714b serves as one electrode, and the conductor 716 a serves as the otherelectrode.

Thus, the capacitor 742 can be formed using a film of the transistor741. The conductor 704 a and the conductor 704 b are preferablyconductors of the same kind, in which case the conductor 704 a and theconductor 704 b can be formed through the same step. Furthermore, theconductor 714 a and the conductor 714 b are preferably conductors of thesame kind, in which case the conductor 714 a and the conductor 714 b canbe formed through the same step.

The capacitor 742 illustrated in FIG. 39C has a large capacitance perarea occupied by the capacitor. Therefore, the EL display deviceillustrated in FIG. 39C has high display quality. Note that although thecapacitor 742 illustrated in FIG. 39C has the structure in which thepart of the insulator 718 a and the part of the insulator 718 b areremoved to reduce the thickness of the region where the conductor 716 aand the conductor 714 b overlap with each other, the structure of thecapacitor according to one embodiment of the present invention is notlimited to the structure. For example, a structure in which a part ofthe insulator 718 c is removed to reduce the thickness of the regionwhere the conductor 716 a and the conductor 714 b overlap with eachother may be used.

An insulator 720 is provided over the transistor 741 and the capacitor742. Here, the insulator 720 may have an opening portion reaching theconductor 716 a that serves as the source electrode of the transistor741. A conductor 781 is provided over the insulator 720. The conductor781 may be electrically connected to the transistor 741 through theopening portion in the insulator 720.

A partition wall 784 having an opening portion reaching the conductor781 is provided over the conductor 781. A light-emitting layer 782 incontact with the conductor 781 through the opening portion provided inthe partition wall 784 is provided over the partition wall 784. Aconductor 783 is provided over the light-emitting layer 782. A regionwhere the conductor 781, the light-emitting layer 782, and the conductor783 overlap with one another serves as the light-emitting element 719.

So far, examples of the EL display device are described. Next, anexample of a liquid crystal display device is described.

FIG. 40A is a circuit diagram illustrating a configuration example of apixel of a liquid crystal display device. A pixel shown in FIGS. 40A and40B includes a transistor 751, a capacitor 752, and an element (liquidcrystal element) 753 in which a space between a pair of electrodes isfilled with a liquid crystal.

One of a source and a drain of the transistor 751 is electricallyconnected to a signal line 755, and a gate of the transistor 751 iselectrically connected to a scan line 754.

One electrode of the capacitor 752 is electrically connected to theother of the source and the drain of the transistor 751, and the otherelectrode of the capacitor 752 is electrically connected to a wiring forsupplying a common potential.

One electrode of the liquid crystal element 753 is electricallyconnected to the other of the source and the drain of the transistor751, and the other electrode of the liquid crystal element 753 iselectrically connected to a wiring to which a common potential issupplied. The common potential supplied to the wiring electricallyconnected to the other electrode of the capacitor 752 may be differentfrom that supplied to the other electrode of the liquid crystal element753.

Note that the description of the liquid crystal display device is madeon the assumption that the plan view of the liquid crystal displaydevice is similar to that of the EL display device. FIG. 40B is across-sectional view of the liquid crystal display device taken alongdashed-dotted line M-N in FIG. 39B. In FIG. 40B, the FPC 732 isconnected to the wiring 733 a via the terminal 731. Note that the wiring733 a may be formed using the same kind of conductor as the conductor ofthe transistor 751 or using the same kind of semiconductor as thesemiconductor of the transistor 751.

For the transistor 751, the description of the transistor 741 isreferred to. For the capacitor 752, the description of the capacitor 742is referred to. Note that the structure of the capacitor 752 in FIG. 40Bcorresponds to, but is not limited to, the structure of the capacitor742 in FIG. 39C.

Note that in the case where an oxide semiconductor is used as thesemiconductor of the transistor 751, the off-state current of thetransistor 751 can be extremely small. Therefore, an electric chargeheld in the capacitor 752 is unlikely to leak, so that the voltageapplied to the liquid crystal element 753 can be maintained for a longtime. Accordingly, the transistor 751 can be kept off during a period inwhich moving images with few motions or a still image are/is displayed,whereby power for the operation of the transistor 751 can be saved inthat period; accordingly a liquid crystal display device with low powerconsumption can be provided. Furthermore, the area occupied by thecapacitor 752 can be reduced; thus, a liquid crystal display device witha high aperture ratio or a high-resolution liquid crystal display devicecan be provided.

An insulator 721 is provided over the transistor 751 and the capacitor752. The insulator 721 has an opening portion reaching the transistor751. A conductor 791 is provided over the insulator 721. The conductor791 is electrically connected to the transistor 751 through the openingportion in the insulator 721.

An insulator 792 serving as an alignment film is provided over theconductor 791. A liquid crystal layer 793 is provided over the insulator792. An insulator 794 serving as an alignment film is provided over theliquid crystal layer 793. A spacer 795 is provided over the insulator794. A conductor 796 is provided over the spacer 795 and the insulator794. A substrate 797 is provided over the conductor 796.

Owing to the above-described structure, a display device including acapacitor occupying a small area, a display device with high displayquality, or a high-resolution display device can be provided.

For example, in this specification and the like, a display element, adisplay device which is a device including a display element, alight-emitting element, and a light-emitting device which is a deviceincluding a light-emitting element can employ various modes or caninclude various elements. For example, the display element, the displaydevice, the light-emitting element, or the light-emitting deviceincludes at least one of a light-emitting diode (LED) for white, red,green, blue, or the like, a transistor (a transistor that emits lightdepending on current), an electron emitter, a liquid crystal element,electronic ink, an electrophoretic element, a grating light valve (GLV),a plasma display panel (PDP), a display element using micro electromechanical systems (MEMS), a digital micromirror device (DMD), a digitalmicro shutter (DMS), an interferometric modulator display (IMOD)element, a MEMS shutter display element, an optical-interference-typeMEMS display element, an electrowetting element, a piezoelectric ceramicdisplay, and a display element including a carbon nanotube. Other thanthe above, display media whose contrast, luminance, reflectivity,transmittance, or the like is changed by electrical or magnetic effectmay be included.

Note that examples of display devices having EL elements include an ELdisplay. Examples of a display device including an electron emitterinclude a field emission display (FED), an SED-type flat panel display(SED: surface-conduction electron-emitter display), and the like.Examples of display devices including liquid crystal elements include aliquid crystal display (e.g., a transmissive liquid crystal display, atransflective liquid crystal display, a reflective liquid crystaldisplay, a direct-view liquid crystal display, or a projection liquidcrystal display). Examples of a display device having electronic ink oran electrophoretic element include electronic paper. In the case of atransflective liquid crystal display or a reflective liquid crystaldisplay, some of or all of pixel electrodes function as reflectiveelectrodes. For example, some or all of pixel electrodes are formed tocontain aluminum, silver, or the like. In such a case, a memory circuitsuch as an SRAM can be provided under the reflective electrodes. Thus,the power consumption can be further reduced.

Note that in the case of using an LED, graphene or graphite may beprovided under an electrode or a nitride semiconductor of the LED.Graphene or graphite may be a multilayer film in which a plurality oflayers are stacked. As described above, provision of graphene orgraphite enables easy formation of a nitride semiconductor thereover,such as an n-type GaN semiconductor including crystals. Furthermore, ap-type GaN semiconductor including crystals or the like can be providedthereover, and thus the LED can be formed. Note that an MN layer may beprovided between the n-type GaN semiconductor including crystals andgraphene or graphite. The GaN semiconductors included in the LED may beformed by MOCVD. Note that when the graphene is provided, the GaNsemiconductors included in the LED can also be formed by a sputteringmethod.

<Electronic Device>

The semiconductor device of one embodiment of the present invention canbe used for display devices, personal computers, or image reproducingdevices provided with recording media (typically, devices whichreproduce the content of recording media such as digital versatile discs(DVDs) and have displays for displaying the reproduced images). Otherexamples of electronic devices that can be equipped with thesemiconductor device of one embodiment of the present invention aremobile phones, game machines including portable game consoles, portabledata terminals, e-book readers, cameras such as video cameras anddigital still cameras, goggle-type displays (head mounted displays),navigation systems, audio reproducing devices (e.g., car audio systemsand digital audio players), copiers, facsimiles, printers, multifunctionprinters, automated teller machines (ATM), and vending machines. FIGS.41A to 41F illustrate specific examples of these electronic devices.

FIG. 41A illustrates a portable game console including a housing 901, ahousing 902, a display portion 903, a display portion 904, a microphone905, a speaker 906, an operation key 907, a stylus 908, and the like.Although the portable game console in FIG. 41A has the two displayportions 903 and 904, the number of display portions included in aportable game console is not limited to this.

FIG. 41B illustrates a portable data terminal including a first housing911, a second housing 912, a first display portion 913, a second displayportion 914, a joint 915, an operation key 916, and the like. The firstdisplay portion 913 is provided in the first housing 911, and the seconddisplay portion 914 is provided in the second housing 912. The firsthousing 911 and the second housing 912 are connected to each other withthe joint 915, and the angle between the first housing 911 and thesecond housing 912 can be changed with the joint 915. An image on thefirst display portion 913 may be switched in accordance with the angleat the joint 915 between the first housing 911 and the second housing912. A display device with a position input function may be used as atleast one of the first display portion 913 and the second displayportion 914. Note that the position input function can be added byproviding a touch panel in a display device. Alternatively, the positioninput function can be added by providing a photoelectric conversionelement called a photosensor in a pixel portion of a display device.

FIG. 41C illustrates a laptop personal computer, which includes ahousing 921, a display portion 922, a keyboard 923, a pointing device924, and the like.

FIG. 41D illustrates an electric refrigerator-freezer, which includes ahousing 931, a door for a refrigerator 932, a door for a freezer 933,and the like.

FIG. 41E illustrates a video camera, which includes a first housing 941,a second housing 942, a display portion 943, operation keys 944, a lens945, a joint 946, and the like. The operation keys 944 and the lens 945are provided for the first housing 941, and the display portion 943 isprovided for the second housing 942. The first housing 941 and thesecond housing 942 are connected to each other with the joint 946, andthe angle between the first housing 941 and the second housing 942 canbe changed with the joint 946. Images displayed on the display portion943 may be switched in accordance with the angle at the joint 946between the first housing 941 and the second housing 942.

FIG. 41F illustrates a car including a car body 951, wheels 952, adashboard 953, lights 954, and the like.

Embodiments of the present invention are described above. Note that oneembodiment of the present invention is not limited to the abovedescription. For example, an example where a semiconductor such as thesemiconductor 406 b includes fluorine or hydrogen is described, but oneembodiment of the present invention is not limited thereto. Depending oncircumstances, the semiconductor such as the semiconductor 406 b mayinclude an element other than fluorine or an element other thanhydrogen; alternatively, the semiconductor such as the semiconductor 406b does not necessarily include fluorine or hydrogen.

EXAMPLE 1

In this example, the measurement results of fluorine concentrations inan oxide semiconductor film to which fluorine is added are shown.

A sample was fabricated in such a manner that a 100-nm-thick siliconoxide film was formed over a silicon substrate by a thermal oxidationmethod, and a 100-nm-thick IGZO film was formed thereon as an oxidesemiconductor film by a sputtering method with the use of an In—Ga—Zn—O(In:Ga:Zn=1:1:1 in atomic ratio) target.

By an ion implantation method, fluorine ions (¹⁹F⁺) with a dose of1.0×10¹⁵ ions/cm² and a dose of 1.0×10¹⁶ ions/cm² were added to thesamples. Note that the accelerating voltage was 20 kV. FIG. 42 shows themeasurement results of the amount of added fluorine in the depthdirection by SIMS.

As shown in FIG. 42, in the case where fluorine with a dose of 1.0×10¹⁵ions/cm² is added, fluorine is contained in the IGZO film at aconcentration of about 3.0×10²⁰ atoms/cm³. Furthermore, in the casewhere fluorine with a dose of 1.0×10¹⁶ ions/cm² is added, fluorine iscontained in the IGZO film at a concentration of about 3.0×10²¹atoms/cm³.

EXAMPLE 2

In this example, the measurement results of sheet resistance values ofan oxide semiconductor film to which fluorine is added are shown.

A sample was fabricated in such a manner that a 100-nm-thick IGZO filmwas formed on a quartz substrate as an oxide semiconductor film by asputtering method with the use of an In—Ga—Zn—O (In:Ga:Zn=1:1:1 inatomic ratio) target.

By an ion implantation method, fluorine ions (¹⁹F ¹) with a dose of1.0×10¹⁴ ions/cm², a dose of 1.0×10¹⁵ ions/cm², and a dose of 1.0×10¹⁶ions/cm² were added to the samples. Note that the accelerating voltagewas 20 kV. FIG. 43 shows measurement results of sheet resistance valuesof the samples fabricated as described above. Note that the measurementupper limit of a sheet resistance measurer is 1×10⁶ Ω/□.

As shown in FIG. 43, as fluorine is added to the IGZO film, the sheetresistance value is increased. Furthermore, when fluorine with a dose of1.0×10¹⁶ ions/cm² is added, the sheet resistance value of the IGZO filmbecomes higher than or equal to 1×10⁶ Ω/□. From this, it is found thatby the addition of fluorine to the IGZO film, the carrier concentrationof the IGZO film decreases and the IGZO film is close to an i-typesemiconductor.

EXAMPLE 3

In this example, the measurement results of defects in an oxidesemiconductor film to which fluorine is added by ESR are shown.

A sample was fabricated in such a manner that a 100-nm-thick IGZO filmwas formed on a quartz substrate as an oxide semiconductor film by asputtering method with the use of an In—Ga—Zn—O (In:Ga:Zn=1:1:1 inatomic ratio) target.

By an ion implantation method, fluorine ions (¹⁹F⁺) with a dose of1.0×10¹⁴ ions/cm², a dose of 1.0×10¹⁵ ions/cm², and a dose of 1.0×10¹⁶ions/cm² were added to the samples. Note that the accelerating voltagewas 20 kV. FIGS. 44A and 44B show the measurement results by ESR of thesamples fabricated as described above.

FIG. 44A shows ESR spectra. As shown in FIG. 44A, as fluorine is addedto the IGZO film, a signal at a g-factor of around 1.93 becomes smaller.In addition, FIG. 44B shows a comparison result between spin densitiesof signals that appear at a g-factor of around 1.93. As shown in FIG.44B, as fluorine is added to the IGZO film, the spin density of thesignal that appears at a g-factor of around 1.93 decreases.

In an IGZO film, a signal that appears at a g-factor of around 1.93 isderived from an oxygen vacancy. Therefore, fluorine is added to the IGZOfilm, whereby oxygen vacancies in the IGZO film can be reduced.

This application is based on Japanese Patent Application serial no.2014-244302 filed with Japan Patent Office on Dec. 2, 2014, the entirecontents of which are hereby incorporated by reference.

What is claimed is:
 1. A semiconductor device comprising: an oxidesemiconductor film including a channel formation region; and a gateelectrode adjacent to the channel formation region with a gateinsulating layer therebetween, wherein the oxide semiconductor filmcontains fluorine in the channel formation region, and wherein afluorine concentration in the channel formation region is higher than orequal to 1×10²⁰ atoms/cm³ and lower than or equal to 1×10²² atoms/cm³.2. The semiconductor device according to claim 1, wherein the gateelectrode is located above the oxide semiconductor film.
 3. Thesemiconductor device according to claim 1, wherein in the oxidesemiconductor film, a fluorine concentration in a region other than thechannel formation region is lower than the fluorine concentration in thechannel formation region.
 4. The semiconductor device according to claim1, wherein the oxide semiconductor film contains at least one selectedfrom indium, zinc, and an element M (an element M is aluminum, gallium,yttrium, or tin).
 5. A module comprising: a printed board; and thesemiconductor device according to claim 1 on the printed board.
 6. Anelectronic device comprising: the semiconductor device according toclaim 1; and a speaker, an operation key, or a battery which iselectrically connected to the semiconductor device.
 7. A semiconductordevice comprising: a first oxide semiconductor film; a second oxidesemiconductor film including a channel formation region over the firstoxide semiconductor film; a third oxide semiconductor film over thesecond oxide semiconductor film; and a gate electrode adjacent to thechannel formation region with a gate insulating layer therebetween,wherein the second oxide semiconductor film contains fluorine in thechannel formation region, and wherein a fluorine concentration in thechannel formation region is higher than or equal to 1×10²⁰ atoms/cm³ andlower than or equal to 1×10²² atoms/cm³.
 8. The semiconductor deviceaccording to claim 7, wherein the gate electrode is located above thethird oxide semiconductor film.
 9. The semiconductor device according toclaim 7, wherein in the second oxide semiconductor film, a fluorineconcentration in a region other than the channel formation region islower than the fluorine concentration in the channel formation region.10. The semiconductor device according to claim 7, wherein the firstoxide semiconductor film and the third oxide semiconductor film containfluorine.
 11. The semiconductor device according to claim 7, wherein thesecond oxide semiconductor film contains at least one selected fromindium, zinc, and an element M (an element M is aluminum, gallium,yttrium, or tin).
 12. A module comprising: a printed board; and thesemiconductor device according to claim 7 on the printed board.
 13. Anelectronic device comprising: the semiconductor device according toclaim 7; and a speaker, an operation key, or a battery which iselectrically connected to the semiconductor device.
 14. A method formanufacturing a semiconductor device, comprising the steps of: formingan oxide semiconductor film over a substrate; forming a source electrodeand a drain electrode in contact with the oxide semiconductor film;adding fluorine to the oxide semiconductor film; forming an insulatingfilm over the oxide semiconductor film, the source electrode, and thedrain electrode; and forming a gate electrode over the insulating film.15. The method for manufacturing a semiconductor device, according toclaim 14, wherein the source electrode and the drain electrode are overthe oxide semiconductor film.
 16. The method for manufacturing asemiconductor device, according to claim 14, wherein the fluorine isadded to the oxide semiconductor film through the insulating film. 17.The method for manufacturing a semiconductor device, according to claim14, wherein the fluorine is added by an ion implantation method.
 18. Themethod for manufacturing a semiconductor device, according to claim 14,wherein the oxide semiconductor film contains at least one selected fromindium, zinc, and an element M (an element M is aluminum, gallium,yttrium, or tin).